SAF7115ET NXP [NXP Semiconductors], SAF7115ET Datasheet - Page 10

• Manufacturer Part Number: SAF7115ET
• Description: Multistandard video decoder with super-adaptive comb filter,
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 4.
SAF7115_1
Product data sheet
Symbol
Real time signals
RTCO
RTS1
RTS0
Clocks
LLC
LLC2
XTALI
XTALO
XTOUT
Boundary scan test
TCK
TDI
TDO
TMS
TRST_N
Test interface
TEST9
TEST8
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
TEST0
Image port (I-port)
ICLK
IDQ
IGP1
Pin description
Pin
HTQFP100
36
35
34
28
29
7
6
4
98
3
2
99
97
-
-
-
-
79
78
77
74
73
44
45
46
49
…continued
TFBGA160
P6
N6
P5
P2
N3
D1
C1
B1
B3
C2
B2
A2
A3
L11
L10
L5
L4
B12
A13
B14
B13
C14
P10
N11
P11
N13
Type
(I/) O/st/pd real time control output
O
O
O
O
I
O
O
I/pu
I/pu
O
I/pu
I/pu
I/pd
AI
AI
I/pu
I/pu
O
I/pu
I/pu
I/pu
O
I/O
O
O
Rev. 01 — 15 October 2008
[1]
Description
real time status or sync information, controlled by subaddresses
11h and 12h
real time status or sync information, controlled by subaddresses
11h and 12h
line-locked system clock output (27 MHz nominal), for backward
compatibility; use pin XCLK for new applications
line locked 1/2 clock output (13.5 MHz nominal) for backward
compatibility; do not use for new applications
input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or
connection of external oscillator with TTL compatible square wave
clock signal
24.576 MHz (32.11 MHz) crystal oscillator output; not connected
if pin XTALI is driven by an external single-ended oscillator
crystal oscillator output signal, auxiliary signal
test clock for boundary scan test (with internal pull-up)
test data input for boundary scan test (with internal pull-up)
test data output for boundary scan test
test mode select for boundary scan test or scan test (with internal
pull-up)
test reset for boundary scan test (active LOW with internal
pull-up); for board design without boundary scan connect
TRST_N to ‘ground’, e.g. through V
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
do not connect, reserved for future extensions and for testing
clock output signal for image port or optional asynchronous back
end clock input
output data qualifier for image port (optional: gated clock output)
general purpose output signal 1; image port (controlled by
subaddresses 84h and 85h); same functions as pin IGP0
[8]
[6]
Multistandard video decoder
SSD(CORE)
[7]
SAF7115
or V
© NXP B.V. 2008. All rights reserved.
SSD(IO)
[7]
[8]
[7]
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