SAA7806H NXP [NXP Semiconductors], SAA7806H Datasheet - Page 43

• Manufacturer Part Number: SAA7806H
• Description: One chip automotive CD audio device
• Manufacturer: NXP [NXP Semiconductors]

Philips Semiconductors
9397 750 13697
Objective data sheet
Fig 25. Subcode output; upsampling disabled
Fig 26. Subcode output; upsampling enabled
IISSubo
WCLK
SYNC
IISSubo
WCLK
SYNC
6.6.7.11 Subcode interface
upsample WCLK period)
2
periods (0.5
upsample WCLK
B7 (start)
(start)
S0
B7
Subcode data is output via the IISSubo (pin V4) port. This data can be sampled using the
I
indicates that the serial subcode line IISSubo contains the MSB of a subcode word. It will
be asserted every six WCLK-periods for half a WCLK-period. If a subcode SYNC is
transferred on the subcode line, this signal will be asserted for a full WCLK period.
During normal operation (upsampling disabled), the subcode output via IISSubo will have
the format as shown in
When upsampling is enabled, the I
upsampled rate. The subcode bit period however will stay at the non-upsampled rate as
shown in
times slower relative to the WCLK. In this case the receiver must use the WCLK divided
by four to sample the subcode.
When slave mode is used, without bclk gating, it is also possible to use the IISSubo output
port as a true single-line interface. In that case the receiver needs to sample the data on
the line with a frequency equal to f
per half WCLK). Two characteristics of the interface can be used in this case to
synchronize the bit and byte detection in the stream in the absence of a SYNC signal:
2
S-bus SYNC signal (see
•
non
The first bit (P-bit) of a subcode-byte is used as a start-bit and therefore always ‘1’ (so
no real P-channel information is available on the interface). Between two subcode
bytes there are four zero-bits; this can be used to identify the start of the subcode
bytes within the stream.
B6
B5
Figure
1 subcode byte every 24 I
B4
26. This means that the IISSubo and SYNC signal will appear to be four
(6 x non upsample WCLK periods)
B6
S1
24
B3
upsample WCLK periods
Rev. 01 — 20 June 2005
Figure
B2
Section 6.6.7.9 “I
B1
25.
2
S-bus bytes
WCLK
B0
B5
2
S-bus interface will run at four times the non
2 (since subcode is output at a rate of one bit
2
S-bus interface” on page
One chip automotive CD audio device
(start)
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
B7
B6
B7 (start)
S0
B5
SAA7806
41). The SYNC
001aab769
B4
001aab770
B6
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