MK61FN1M0VMD12 FREESCALE [Freescale Semiconductor, Inc], MK61FN1M0VMD12 Datasheet - Page 54

• Manufacturer Part Number: MK61FN1M0VMD12
• Description: K61 Sub-Family Data Sheet
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Peripheral operating requirements and behaviors
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
6.6.2 CMP and 6-bit DAC electrical specifications
1. Typical hysteresis is measured with input voltage range limited to 0.6 to V
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
3. 1 LSB = V
54
Symbol
V
V
PGA reference voltage and gain setting.
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
I
I
I
DAC6b
V
V
CMPOh
DNL
V
DDHS
CMPOl
t
t
DDLS
INL
V
DHS
DLS
AIN
AIO
DD
H
reference
Supply voltage
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
Analog input offset voltage
Analog comparator hysteresis
Output high
Output low
Propagation delay, high-speed mode (EN=1,
PMODE=1)
Propagation delay, low-speed mode (EN=1,
PMODE=0)
Analog comparator initialization delay
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
Description
Table 32. Comparator and 6-bit DAC electrical specifications
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
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K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
1
2
Preliminary
V
V
SS
DD
1.71
–0.5
–0.3
Min.
20
80
—
—
—
—
—
—
—
—
—
—
– 0.3
– 0.5
DD
-0.6V.
Typ.
250
10
20
30
50
—
—
—
—
—
—
—
—
—
—
5
7
Freescale Semiconductor, Inc.
Max.
V
200
200
600
3.6
0.5
0.5
0.3
20
20
40
—
—
—
—
—
—
DD
LSB
LSB
Unit
mV
mV
mV
mV
mV
μA
μA
μA
ns
ns
μs
V
V
V
V
3