MM908E622ACDWBR2 FREESCALE [Freescale Semiconductor, Inc], MM908E622ACDWBR2 Datasheet - Page 28

• Manufacturer Part Number: MM908E622ACDWBR2
• Description: Integrated Quad Half-bridge, Triple High Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

HO Input Interrupt
change of the H0F flag (rising or falling edge on the enabled
input). The interrupt function is available if the input is
selected as General Purpose, or as 2pin Hallsensor input.
The interrupt is maskable with the H0IE bit in the Interrupt
Mask Register.
L0 input Interrupt
change of the L0F flag (rising or falling edge). The interrupt is
maskable with the L0IE bit in the interrupt mask register.
INTERRUPT FLAG REGISTER (IFR)
L0IF - L0 Input Flag Bit
L0 input. Clear L0IF by writing a logic [1] to L0IF. Reset clears
the L0IF bit. Writing a logic [0] to L0IF has no effect.
H0IF - H0 Input Flag Bit
H0 input. Clear H0IF by writing a logic [1] to H0IF. Reset
clears the H0IF bit. Writing a logic [0] to H0IF has no effect.
LINIF - LIN Flag Bit
the bus was dominant longer than TpropWL. Clear LINIF by
writing a logic [1] to LINIF. Reset clears the LINIF bit. Writing
a logic [0] to LINIF has no effect.
HTIF - High Temperature Flag Bit
Clear HTIF by writing a logic [1] to HTIF. If a high temperature
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908E622
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Reset
Read
Write
The H0 interrupt flag H0IF is set in run mode by a state
During Stop and Sleep mode the H0I circuitry is disabled.
The L0 interrupt flag L0IF is set in run mode by a state
This read/write flag is set on a falling or rising edge at the
This read/write flag is set on a falling or rising edge at the
This read/write flag is set if a rising edge is detected and
This read/write flag is set on high temperature condition.
1 = rising or falling edge on L0 input detected
0 = no state change on L0 input detected
1 = state change on the hallflags detected
0 = no state change on the hallflags detected
1 = LIN bus interrupt has occurred
0 = not LIN bus interrupt occurred since last clear
Bit7
L0IF
0
Register Name and Address: IFR - $0A
H0IF
6
0
LINIF
5
0
4
0
0
HTIF
3
0
LVIF
2
0
HVIF
1
0
PSFIF
Bit0
0
condition is still present while writing a logical one to HTIF,
the writing has no effect. Therefore, a high temperature
interrupt cannot be lost due to an inadvertent clearing of
HTIF. Reset clears the HTIF bit. Writing a logic [0] to HTIF
has no effect.
LVIF - Low Voltage Flag Bit
LVIF by writing a logic [1] to LVIF. If a low voltage condition
is still present while writing a logical one to LVIF, writing has
no effect. Therefore, a low voltage interrupt cannot be lost
due to inadvertent clearing of LVIF. Reset clears the LVIF bit.
Writing a logic [0] to LVIF has no effect.
HVIF - High Voltage Flag Bit
Clear HVIF by writing a logic [1] to HVIF. If a high voltage
condition is still present while writing a logical one to HVIF,
the writing has no effect. Therefore, a high voltage interrupt
cannot be lost due to an inadvertent clearing of HVIF. Reset
clears the HVIF bit. Writing a logic [0] to HVIF has no effect.
PSFIF - Power Stage Fail Bit
power outputs (HBx, HSx, HVDD, EC, H0). Reset clears the
PSFIF bit. Clear this flag, by writing a logic [1] to the
appropriate fail flag.
This read/write flag is set on low voltage condition. Clear
This read/write flag is set on a high voltage condition.
This read-only flag is set on a fail condition on one of the
H0OCF
HVDDOCF
HB1OC
HB2OC
HB3OC
HB4OC
HS1OC
HS2OC
HS3OC
ECOLF
ECOCF
Figure 14. Principal Implementation of the PSFIF
1 = high temperature condition has occurred
0 = high temperature condition has not occurred
1 = low voltage condition has occurred
0 = low voltage condition has not occurred
1 = high voltage condition has occurred
0 = high voltage condition has not occurred
1 = power stage fail condition has occurred
0 = power stage fail condition has not occurred
Analog Integrated Circuit Device Data
HVDDOCF
H0OCF
HBFF
HSFF
ECFF
Freescale Semiconductor
PSFIF