MM908E622ACDWBR2 FREESCALE [Freescale Semiconductor, Inc], MM908E622ACDWBR2 Datasheet - Page 31

• Manufacturer Part Number: MM908E622ACDWBR2
• Description: Integrated Quad Half-bridge, Triple High Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

POR— Power On Reset Bit
by writing a logic “1” to this location.
PINR— Reset Forced from External Reset Pin Bit
external reset RST_A pin. The bit is cleared by writing a logic
“1” to this location.
WDR— Watch Dog Reset Bit
wrong watchdog timer reset. Clear WDR by writing a logic “1”
to WDR.
LIN PHYSICAL LAYER
communication in automotive applications. The LIN physical
layer is designed to meet the LIN physical layer specification.
limitation and thermal shutdown. An internal pullup resistor
with a serial diode structure is integrated, so no external
pullup components are required for the application in a slave
mode. The fall time from dominant to recessive, and the rise
time from recessive to dominant is controlled. The symmetry
between both slew rate controls is guaranteed.
10 and 20kBit/s, as well as high baud rates for test and
programming. The slew rate can be adapted with 2 bits
SRS[1:0] in the System Control Register. The initial slew rate
is optimized for 20kBit/s.
Analog Integrated Circuit Device Data
Freescale Semiconductor
Read
Write
POR
This read/write bit is set after power on. The bit is cleared
This read/write bit is set after a reset was forced on the
This read/write flag is set due to watchdog timeout or a
The LIN bus pin provides a physical layer for single-wire
The LIN driver is a low side MOSFET with internal current
The slew rate can be selected for optimized operation at
1 = Reset due to power on
0 = no power on reset
1 = reset source is external reset pin
0 = no external reset
1 = reset source is watchdog
0 = no watchdog reset
POR
Bit7
1
Register Name and Address: RSR - $0D
PINR
6
0
WDR
5
0
HTR
4
0
LVR
3
0
2
0
0
ANALOG DIE INPUTS / OUTPUTS
LINWF LOWF
1
0
Bit0
0
HTR— High Temperature Reset Bit
certain value. The bit is cleared by writing a logic “1” to this
location.
LVR— Low Voltage Reset Bit
from the main voltage regulator falls below a certain value. Bit
is cleared by writing a logic “1” to this location.
LINWF— LIN Wake-up Flag
wake-up. Bit is cleared by writing a logic “1” to this location.
L0WF— L0 Wake-up Flag
wake-up. Bit is cleared by writing a logic “1” to this location.
external disturbance, guaranteeing communication during
external disturbance.
PSON bit in the System Control Register (SYSCTL).
LINCL bit in the System Status Register (SYSSTAT) is set
and the LIN transceiver is disabled after a certain time.
LIN bus shorts to Ground, or LIN bus leakage during low
power mode, the internal pull-up resistor on the LIN pin is
disconnected from VSUP and a small current source keeps
the LIN bus at recessive level. In case of a LIN bus short to
GND, this feature will reduce the current consumption in
STOP and SLEEP modes.
This read/write bit is set if the chip temperature exceeds a
This read/write bit is set if the external V
This read/write bit is set if a bus activity was the case of an
This read/write bit is set if a event on the L0 pin caused an
The LIN pin offers high susceptibility immunity level from
The LIN transmitter circuitry is enabled by setting the
If the transmitter works in the current limitation region, the
For improved performance and safe behavior when the
1 = reset due to high temperature condition
0 = no high temperature reset
1 = reset due to low voltage condition
0 = no low voltage reset
1 = Wake-up due to bus activity
0 = no wake-up due to bus activity
1 = Wake-up due to L0 pin
0 = no Wake-up due to L0 pin
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
DD
voltage coming
908E622
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