CY8C38_1105 CYPRESS [Cypress Semiconductor], CY8C38_1105 Datasheet - Page 61

• Manufacturer Part Number: CY8C38_1105
• Description: Programmable System-on-Chip (PSoC) Multiply and divide instructions
• Manufacturer: CYPRESS [Cypress Semiconductor]

8.11.1 Down Mixer
The SC/CT block can be used as a mixer to down convert an
input signal. This circuit is a high bandwidth passive sample
network that can sample input signals up to 14 MHz. This
sampled value is then held using the opamp with a maximum
clock rate of 4 MHz. The output frequency is at the difference
between the input frequency and the highest integer multiple of
the Local Oscillator that is less than the input.
8.11.2 First Order Modulator – SC Mode
A first order modulator is constructed by placing the SC/CT block
in an integrator mode and using a comparator to provide a 1-bit
feedback to the input. Depending on this bit, a reference voltage
is either subtracted or added to the input signal. The block output
is the output of the comparator and not the integrator in the
modulator case. The signal is downshifted and buffered and then
processed by a decimator to make a delta-sigma converter or a
counter to make an incremental converter. The accuracy of the
sampled data from the first-order modulator is determined from
several factors.
The main application for this modulator is for a low-frequency
ADC with high accuracy. Applications include strain gauges,
thermocouples, precision voltage, and current measurement.
9. Programming, Debug Interfaces,
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
Three interfaces are available: JTAG, SWD, and SWV. JTAG and
SWD support all programming and debug features of the device.
JTAG also supports standard JTAG scan chains for board level
test and chaining multiple JTAG devices to a single JTAG
connection.
For more information on PSoC 3 Programming, refer to the
application note
PSoC
Complete Debug on Chip (DoC) functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
Document Number: 001-11729 Rev. *S
Resources
®
3.
AN62391 - In-System Programming for
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV
interfaces are fully compatible with industry standard third party
tools.
All DOC circuits are disabled by default and can only be enabled
in firmware. If not enabled, the only way to reenable them is to
erase the entire device, clear flash protection, and reprogram the
device with new firmware that enables DOC. Disabling DOC
features, robust flash protection, and hiding custom analog and
digital functionality inside the PSoC device provide a level of
security not possible with multichip application solutions.
Additionally, all device interfaces can be permanently disabled
(Device Security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device. Permanently
disabling interfaces is not recommended in most applications
because you cannot access the device later. Because all
programming, debug, and test interfaces are disabled when
device security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
Table 9-1. Debug Configurations
9.1 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four or five
pins (the nTRST pin is optional). The JTAG clock frequency can
be up to 8 MHz, or 1/3 of the CPU clock frequency for 8 and 16-bit
transfers, or 1/5 of the CPU clock frequency for 32-bit transfers,
whichever is least. By default, the JTAG pins are enabled on new
devices but the JTAG interface can be disabled, allowing these
pins to be used as General Purpose I/O (GPIO) instead. The
JTAG interface is used for programming the flash memory,
debugging, I/O scan chains, and JTAG device chaining.
All debug and trace disabled
JTAG
SWD
SWV
SWD + SWV
Debug and Trace Configuration
PSoC
®
3: CY8C38 Family
GPIO Pins Used
Data Sheet
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