MC68HC08AZ60CFU MOTOROLA [Motorola, Inc], MC68HC08AZ60CFU Datasheet - Page 282

• Manufacturer Part Number: MC68HC08AZ60CFU
• Description: Advance Information
• Manufacturer: MOTOROLA [Motorola, Inc]

I/O Ports
MC68HC08AZ60 — Rev 1.0
282
NOTE:
DDRA[7:0] — Data Direction Register A Bits
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 4
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
operation of the port A pins.
Freescale Semiconductor, Inc.
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
For More Information On This Product,
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
shows the port A I/O logic.
Go to: www.freescale.com
I/O Ports
RESET
Figure 4. Port A I/O Circuit
DDRAx
PTAx
Table 1
summarizes the
MOTOROLA
4-ioports
PTAx