ISL6255 INTERSIL [Intersil Corporation], ISL6255 Datasheet
ISL6255
Available stocks
Related parts for ISL6255
ISL6255 Summary of contents
Page 1
... Highly Integrated Battery Charger with Automatic Power Source Selector for Notebook Computers The ISL6255, ISL6255A is a highly integrated battery charger controller for Li-Ion/Li-Ion polymer batteries. High Efficiency is achieved by a synchronous buck topology and the use of a MOSFET, instead of a diode, for selecting power from the adapter or battery ...
Page 2
... VREF 7 CHLIM ISL6255, ISL6255A CSOP 20 CSIN 19 CSIP 18 SGATE 17 BGATE 16 PHASE 15 UGATE 13 14 ISL6255, ISL6255A (28 LD QSOP) TOP VIEW 1 28 DCPRN DCIN 2 27 ACPRN VDD 3 26 CSON ACSET 4 25 CSOP DCSET 5 24 CSIN CSIP CELLS 7 22 SGATE ...
Page 3
... TRIP POINTS ACSET Threshold ACSET Input Bias Current Hysteresis ACSET Input Bias Current ACSET Input Bias Current DCSET Threshold 3 ISL6255, ISL6255A Thermal Information Thermal Resistance QFN Package (Notes 4, 5 QSOP Package (Note ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2 Junction Temperature Range .-10°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . .-10° ...
Page 4
... VDDP-PGND=5V, 500mA sink current VDDP-PGND=5V, LGATE=2.5V Guaranteed by design 0 < CSOP < 18V 0 < CSON < 18V ISL6255: CHLIM=3.3V ISL6255A: CHLIM=3.3V ISL6255: CHLIM=2.0V ISL6255A: CHLIM=2.0V ISL6255: CHLIM=0.2V ISL6255A: CHLIM=0.2V CHLIM=GND or 3.3V, DCIN=0V CHLIM rising Guarantee by design CSIP=CSIN=25V 0 < CSIN < DCIN, Guaranteed by design =1µF, I =0mA, T =-10°C to +100°C, ...
Page 5
... CSIP-SGATE Voltage Low CSIP-CSIN Threshold for CSIP-SGATE Going High CSIP-CSIN Threshold Hysteresis LOGIC INTERFACE EN Input Voltage Range EN Threshold Voltage EN Input Bias Current ACPRN Sink Current 5 ISL6255, ISL6255A TEST CONDITIONS ACLIM=VREF ACLIM=Float ACLIM=GND ACLIM= VREF ACLIM=GND CELLS=VDD CSIP-BGATE=3V CSIP-BGATE=5V DCIN=12V, CSON Rising ...
Page 6
... FIGURE 1. VDD LOAD REGULATION CSIP-CSIN (mV) FIGURE 3. ICM ACCURACY vs AC ADAPTER CURRENT 6 ISL6255, ISL6255A TEST CONDITIONS ACPRN=5V DCPRN=0.4V DCPRN=5V CSIP-CSIN=100mV CSIP-CSIN=75mV CSIP-CSIN=50mV DCIN=20V, 4S2P Li-Battery, T VDD=5.075V VDD=5.075V EN=0 EN 100 FIGURE 4. SYSTEM EFFICIENCY vs CHARGE CURRENT =1µ ...
Page 7
... Typical Operating Performance FIGURE 5. AC & DC ADAPTER DETECTION FIGURE 7. CHARGER ENABLE & SHUTDOWN CHLIM=0.2V CHLIM=0.2V CSON=8V CSON=8V FIGURE 9. AC ADAPTER REMOVAL 7 ISL6255, ISL6255A DCIN=20V, 4S2P Li-Battery, T =25°C, unless otherwise noted. (Continued) A DCIN DCIN 10V/div 10V/div ACSET ACSET 1V/div 1V/div DCSET ...
Page 8
... AC adapter output voltage at DCIN, BGATE is driven to low and selects the battery as the power source. LGATE LGATE is the low side MOSFET gate drive output; swing between 0V and VDDP. 8 ISL6255, ISL6255A DCIN=20V, 4S2P Li-Battery, T =25°C, unless otherwise noted. (Continued) A SGATE-CSIP SGATE-CSIP ...
Page 9
... MOSFET. VDD VDD is an internal LDO output to supply IC analog circuit. Connect a 1µF ceramic capacitor to ground. 9 ISL6255, ISL6255A VDDP VDDP is the supply voltage for the low-side MOSFET gate driver. Connect a 4.7Ω resistor to VDD and a 1µF ceramic capacitor to power ground. ...
Page 10
... ISL6255, ISL6255A SGATE SGATE CSIP CSIP ICM ACSET ACPRN + + + + + + - - - - - 1.27V Adapter Adapter Adapter Adapter ACLIM Current Limit Set Current Limit Set Current Limit Set Current Limit Set 2.1V 2.1V 2.1V 2.1V Min Min Min Min Min Min Min ICOMP + + + + Voltage Voltage Voltage Voltage Voltage Voltage ...
Page 11
... TRICKLE TRICKLE TRICKLE TRICKLE CHARGE CHARGE CHARGE CHARGE FIGURE 15. ISL6255, ISL6255A TYPICAL APPLICATION CIRCUIT WITH FIXED CHARGING PARAMETERS 11 ISL6255, ISL6255A 0.1 0.1µF 0.1 0.1 CSON CSON CSON CSON SGATE SGATE SGATE SGATE CSIP ...
Page 12
... SCL SCL SCL SCL SDL SDL SDL SDL A/D INPUT A/D INPUT A/D INPUT A/D INPUT GND GND GND GND FIGURE 16. ISL6255, ISL6255A TYPICAL APPLICATION CIRCUIT WITH µP CONTROL AND AIRCRAFT POWER SUPPORT 12 ISL6255, ISL6255A VDD VDD VDD VDD 0.1 0.1 0.1µ 0.1 CSON ...
Page 13
... A high efficiency synchronous buck converter is used to control the charging voltage and charging current up to 10A. The ISL6255, ISL6255A has input current limiting and analog inputs for setting the charge current and charge voltage; CHLIM inputs are used to control charge current and VADJ inputs are used to control charge voltage ...
Page 14
... By using the input current limiter, the current capability of the AC adapter can be lowered, reducing CELL NUMBER system cost. 4 The ISL6255, ISL6255A limits the battery charge current 3 when the input current-limit threshold is exceeded, ensuring the battery charger does not load down the AC adapter 2 voltage ...
Page 15
... VDD through an external low pass filter. Bypass VDDP and VDD with a 1µF capacitor. Shutdown The ISL6255, ISL6255A features a low-power shutdown mode. Driving EN low shuts down the ISL6255, ISL6255A. In shutdown, the DC/DC converter is disabled, and VCOMP 15 ISL6255, ISL6255A and ICOMP are pulled to ground. The ICM, ACPRN and DCPRN outputs continue to function ...
Page 16
... MOSFET that has the conduction losses equal to the switching losses. Ensure that ISL6255, ISL6255A LGATE gate driver can supply sufficient gate current to prevent it from conduction, which is due to the injected current into the drain-to-source parasitic ...
Page 17
... GATE ≤ Q GATE ISL6255, ISL6255A Where I less than 24mA. Substituting I into the previous equation yields that the total gate charge should be less than 80nC. Therefore, the ISL6255, ISL6255A easily drives the battery charge current ...
Page 18
... R12 1.87k Ω , ± 1%, (0805) R13 Loop Compensation Design ISL6255, ISL6255A uses a constant frequency current mode control architecture to achieve fast loop transient response. Accurate current sensing resistors in series with the output inductor is used to regulate the charge current, and the sensed current signal is injected into the voltage loop to achieve current mode control to simplify the loop compensation design ...
Page 19
... Therefore, choose 1 1 voltage loop compensator: R =10K ISL6255, ISL6255A PCB Layout Considerations Power and Signal Layers Placement on the PCB As a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on COMP COMP the opposite side of the board example, layer arrangement on a 4-layer board is shown below: 1 ...
Page 20
... This pin stays high at enable mode and low at idle mode and is relatively robust. Enable signals should refer to the signal ground. 20 ISL6255, ISL6255A DCIN Pin This pin connects to AC adapter output voltage, and should be less noise sensitive. Copper Size for the Phase Node The capacitance of PHASE should be kept very low to minimize ringing ...
Page 21
... CORNER REF. OPTION 4X BOTTOM VIEW SECTION "C-C" TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE 21 ISL6255, ISL6255A L28.5x5 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE SYMBOL 0.10 C 0.08 C ...
Page 22
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 ISL6255, ISL6255A M28.15 28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE M ...