ISL6313 INTERSIL [Intersil Corporation], ISL6313 Datasheet - Page 20

• Manufacturer Part Number: ISL6313
• Description: Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications
• Manufacturer: INTERSIL [Intersil Corporation]

Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
efficiency from the reduced freewheeling time of the lower
MOSFET body-diode conduction, and to prevent the upper and
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V (forward/reverse
inductor current). At this time the UGATE is released to rise. An
auto-zero comparator is used to correct the r
phase voltage preventing false detection of the -0.3V phase
level during r
current, the UGATE is released after 35ns delay of the LGATE
dropping below 0.5V. When LGATE first begins to transition
low, this quick transition can disturb the PHASE node and
cause a false trip, so there is 20ns of blanking time once
LGATE falls until PHASE is monitored.
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
FIGURE 11. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
20nC
DS(ON)
0.1
VOLTAGE
0.2
50nC
conduction period. In the case of zero
Q
GATE
0.3
= 100nC
ΔV
0.4
20
BOOT_CAP
0.5
0.6
(V)
DS(ON)
0.7
0.8
drop in the
0.9
1.0
ISL6313
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value can be
chosen from Equation 18:
where Q
at V
control MOSFETs. The ΔV
allowable droop in the rail of the upper gate drive.
Gate Drive Voltage Versatility
The ISL6313 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC and the VID pins. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, the controller asserts
PGOOD.
Enable and Disable
While in shutdown mode, the LGATE and UGATE signals
are held low to assure the MOSFETs remain off. The
following input conditions must be met, for both Intel and
AMD modes of operation, before the ISL6313 is released
C
Q
FIGURE 12. POWER SEQUENCING USING THRESHOLD-
BOOT_CAP
GATE
GS1
FAULT LOGIC
CIRCUIT
SOFT-START
POR
=
G1
gate-source voltage and N
AND
Q
---------------------------------- N
G1
is the amount of gate charge per upper MOSFET
ISL6313 INTERNAL CIRCUIT
≥
V
SENSITIVE ENABLE (EN) FUNCTION
------------------------------------- -
ΔV
⋅
GS1
PVCC
BOOT_CAP
Q
GATE
⋅
Q1
ENABLE
COMPARATOR
BOOT_CAP
+
-
0.85V
Q1
term is defined as the
is the number of
VCC
PVCC
EN
EXTERNAL CIRCUIT
10.7kΩ
1.40kΩ
March 5, 2007
+12V
(EQ. 18)
FN6448.0