ISL6333A INTERSIL [Intersil Corporation], ISL6333A Datasheet - Page 24

• Manufacturer Part Number: ISL6333A
• Description: Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light Load Efficiency Enhancements for Intel VR11.1 Applications
• Manufacturer: INTERSIL [Intersil Corporation]

TABLE 2. VR11 VOLTAGE IDENTIFICATION CODES (Continued)
Voltage Regulation
The integrating compensation network shown in Figure 7,
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the controllers to include the
combined tolerances of each of these elements.
The output of the error amplifier, V
modulator waveform to generate the PWM signals. The
PWM signals control the timing of the Internal MOSFET
drivers and regulate the converter output so that the voltage
at FB is equal to the voltage at REF. This will regulate the
output voltage to be equal to Equation 8. The internal and
external circuitry that controls voltage regulation is illustrated
in Figure 7.
The controllers incorporate an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference
point resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote sense output, V
connected to the inverting input of the error amplifier through
an external resistor.
Load Line (Droop) Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
V
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
OUT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
=
0
0
0
0
0
0
0
0
0
0
0
0
1
1
V
REF
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
V
OFS
0
0
0
0
0
0
0
0
0
1
1
1
1
1
–
V
DROOP
0
1
1
1
1
1
1
1
1
0
0
0
1
1
24
COMP
1
0
0
0
0
1
1
1
1
0
0
0
1
1
ISL6333, ISL6333A, ISL6333B, ISL6333C
, is compared to the
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
DIFF
0.56875
0.56250
0.55625
0.55000
0.54375
0.53750
0.53125
0.52500
0.51875
0.51250
0.50625
0.50000
OFF
OFF
VDAC
(EQ. 8)
, is
the output voltage can effectively be level shifted in a
direction which works to achieve the load line regulation
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output voltage spike that
results from fast load current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 7, a current proportional to the average
current of all active channels, I
through a load line regulation resistor R
voltage drop across R
effectively creating an output voltage droop with a steady-state
value defined as Equation 9:
The regulated output voltage is reduced by the droop voltage
V
derived by combining Equations 6, 7, 8, and 9.
V
V
DROOP
DROOP
OUT
FIGURE 7. OUTPUT VOLTAGE AND LOAD-LINE
R
C
R
FB
C
C
=
. The output voltage as a function of load current is
V
V
V
EXTERNAL CIRCUIT
=
OUT
OUT
REF
+
-
(V
I
AVG
DROOP
REGULATION WITH OFFSET ADJUSTMENT
-
+
–
V
⋅
OFS
R
+ V
IDROOP
C
FB
FB
REF
OFS
COMP
VDIFF
RGND
–
VSEN
REF
⎛
⎜
⎝
FB
is proportional to the output current,
I
------------ -
)
OUT
N
AVG
⋅
AMPLIFIER
-------------- -
R
DCR
ISL6333 INTERNAL CIRCUIT
ERROR
I
, flows from the IDROOP pin
AVG
SET
⋅
1k
FB
400
--------- - R
I
VID DAC
OFS
3
. The resulting
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
+
-
⋅
+
-
FB
⎞
⎟
⎠
October 8, 2010
V
COMP
(EQ. 10)
(EQ. 9)
FN6520.3