SAF-XC164GM-8F20F INFINEON [Infineon Technologies AG], SAF-XC164GM-8F20F Datasheet
SAF-XC164GM-8F20F
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SAF-XC164GM-8F20F Summary of contents
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XC164GM ...
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... Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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XC164GM ...
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XC164GM Data Sheet Revision History: V1.0, 2005-11 Previous Version: None Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will ...
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Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Single-Chip Microcontroller with C166SV2 Core XC166 Family 1 Summary of Features • High Performance 16-bit CPU with 5-Stage Pipeline – Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) – 1-Cycle Multiplication (16 – 1-Cycle Multiply-and-Accumulate ...
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General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis • On-Chip Bootstrap Loader • On-Chip Debug Support via JTAG Interface Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the ...
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... Table 1-1 XC164GM Derivative Synopsis 1) Derivative SAF-XC164GM-8F40F SAF-XC164GM-8F20F SAF-XC164GM-4F40F SAF-XC164GM-4F20F 1) This Data Sheet is valid for devices starting with and including design step AA. Data Sheet Temp. Program Range Memory -40 85°C 64 Kbytes Flash -40 85°C 32 Kbytes Flash 6 XC164GM Derivatives Summary of Features On-Chip RAM ...
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General Device Information The XC164GM derivatives are high-performance members of the Infineon XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and ...
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Pin Configuration and Definition The pins of the XC164GM are described in detail in alternate functions. Figure 2-2 location on the 4 sides of the package. E* marks pins to be used as alternate external interrupt inputs. 64 P1H.0/EX0IN/CC23IO ...
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... XC164GM. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 CPU clock cycles. Note: The reset duration must be sufficient to let the hardware configuration signals settle. External circuitry must guarantee low-level at the RSTIN pin at least until both power supply voltages have reached the operating range ...
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Table 2-1 Pin Definitions and Functions (cont’d) Sym- Pin Input bol Num. Outp. Port 9 43-48 IO P9 P9.1 44 I/O O P9 P9.3 46 I/O O P9.4 47 I/O P9.5 48 ...
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Table 2-1 Pin Definitions and Functions (cont’d) Sym- Pin Input bol Num. Outp. TRST 62 I Port 3 28- P3.5 ...
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Table 2-1 Pin Definitions and Functions (cont’d) Sym- Pin Input bol Num. Outp. PORT1 1-6, IO 49-56 P1L.7 56 I/O P1H I/O P1H I/O P1H I/O P1H I/O I P1H.4 5 I/O ...
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Table 2-1 Pin Definitions and Functions (cont’d) Sym- Pin Input bol Num. Outp 27, - DDP 40 The CAN interface lines are assigned to port P9 under software control. Data ...
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Functional Description The architecture of the XC164GM combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum ...
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Memory Subsystem and Organization The memory space of the XC164GM is configured in a von Neumann architecture, which means that all internal and external resources, such as code memory, data memory, registers and I/O ports, are organized within the ...
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R15) and/or byte wide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs). The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR, ...
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Central Processing Unit (CPU) The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three ...
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Also multiplication and most MAC instructions execute in one single cycle. All multiple-cycle instructions have been optimized so that ...
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Interrupt System With an interrupt response time of typically 8 CPU clocks (in case of internal program execution), the XC164GM is capable of reacting very fast to the occurrence of non- deterministic events. The architecture of the XC164GM supports ...
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Table 3-2 XC164GM Interrupt Nodes Source of Interrupt or PEC Service Request EX0IN EX1IN EX2IN EX3IN EX4IN EX5IN CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM ...
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Table 3-2 XC164GM Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error ASC0 Autobaud SSC0 Transmit SSC0 Receive SSC0 Error PLL/OWD ...
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Table 3-2 XC164GM Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned node Unassigned ...
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The XC164GM also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
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On-Chip Debug Support (OCDS) The On-Chip Debug Support system provides a broad range of debug and emulation features built into the XC164GM. The user software running on the XC164GM can thus be debugged within the target system environment. The ...
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Capture/Compare Unit (CAPCOM2) The CAPCOM unit supports generation and control of timing sequences channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered mode). The CAPCOM unit is typically used to ...
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In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a ...
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C C T7IN T6OUF CCxIO CCxIO CCxIO T6OUF CAPCOM2 provides channels … 31. (see signals CCxIO and CCxIRQ) Figure 3-3 CAPCOM2 Unit Block Diagram Data Sheet Reload Reg. T7REL T7 Input Timer T7 ...
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General Purpose Timer (GPT12E) Unit The GPT12E unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, ...
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T3CON.BPS1 GPT T2IN T2 Mode Control T2EUD T3 T3IN Mode Control T3EUD T4IN T4 Mode Control T4EUD Figure 3-4 Block Diagram of GPT1 With its maximum resolution of 2 system clock cycles, the GPT2 module provides ...
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Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, ...
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T6CON.BPS2 GPT T5 T5IN Mode Control CAPIN CAPREL Mode Control T3IN/ T3EUD T6 Mode Control T6IN Figure 3-5 Block Diagram of GPT2 Data Sheet Basic Clock GPT2 Timer T5 U/D Clear Capture GPT2 CAPREL Reload Clear ...
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Real Time Clock The Real Time Clock (RTC) module of the XC164GM is directly clocked via a separate clock driver with the prescaled on-chip main oscillator frequency ( therefore independent from the selected clock generation mode of the XC164GM. ...
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System clock to determine the current time and date, optionally during idle mode, sleep mode, and power down mode • Cyclic time based interrupt, to provide a system time tick independent of CPU frequency and other resources, e.g. to ...
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A/D Converter For analog signal measurement, a 10-bit A/D converter with 14 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) ...
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Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial communication with other microcontrollers, processors, terminals or external peripheral components. They are upward compatible with the serial ports of the Infineon 8-bit microcontroller families and support full-duplex ...
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High Speed Synchronous Serial Channels (SSC0/SSC1) The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and half- duplex synchronous communication. It may be configured so it interfaces with serially linked peripheral components, full SPI functionality is supported. A dedicated ...
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TwinCAN Module The integrated TwinCAN module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip TwinCAN module can receive and transmit standard frames with 11-bit ...
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Summary of Features • CAN functionality according to CAN specification V2.0 B active • Data transfer rate Mbit/s • Flexible and powerful message transfer control and error handling capabilities • Full-CAN functionality and Basic CAN functionality for ...
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... Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can be disabled until the EINIT instruction has been executed (compatible mode can be disabled and enabled at any time by executing instructions DISWDT and ENWDT (enhanced mode). Thus, the chip’ ...
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Clock Generation The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers to generate the clock signals for the XC164GM with high flexibility. The master clock is the reference clock signal, and is used for TwinCAN and ...
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Parallel Ports The XC164GM provides I/O lines which are organized into three input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via ...
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Power Management The XC164GM provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • Power Saving Modes switch the XC164GM ...
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Instruction Set Summary Table 3-6 lists the instructions of the XC164GM in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and ...
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Table 3-6 Instruction Set Summary (cont’d) Mnemonic Description ASHR Arithmetic (sign bit) shift right direct word GPR MOV(B) Move word (byte) data MOVBS/Z Move byte operand to word op. with sign/zero extension JMPA/I/R Jump absolute/indirect/relative if condition is met JMPS ...
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Table 3-6 Instruction Set Summary (cont’d) Mnemonic Description CoMUL/CoMAC Multiply (and accumulate) CoADD/CoSUB Add/Subtract Co(A)SHR/CoSHL (Arithmetic) Shift right/Shift left CoLOAD/STORE Load accumulator/Store MAC register CoCMP/MAX/MIN Compare (maximum/minimum) CoABS/CoRND Absolute value/Round accumulator CoMOV/NEG/NOP Data move/Negate accumulator/Null operation Data Sheet Functional Description ...
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Electrical Parameters 4.1 General Parameters Table 4-1 Absolute Maximum Ratings Parameter Storage temperature Junction temperature V Voltage on pins with DDI respect to ground ( Voltage on pins with DDP respect to ground ( V ...
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... Active mode DDP DDI V Reference voltage 5)6) mA Per IO pin mA Per analog input 5)6) pin - – > – I < – > – < Pin drivers in default mode C SAB-XC164… C SAF-XC164… C SAK-XC164… V1.0, 2005- ...
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Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified ...
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DC Parameters Table 4-3 DC Characteristics (Operating Conditions apply) Parameter Symbol V Input low voltage TTL (all except XTAL1) V Input low voltage XTAL1 V Input low voltage (Special Threshold) V Input high voltage TTL (all except XTAL1) V ...
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Table 4-3 DC Characteristics (Operating Conditions apply) Parameter Symbol I XTAL1 input current 11) C Pin capacitance (digital inputs/outputs) 1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions. For signal levels outside these ...
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Table 4-5 Power Consumption XC164GM (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active Pad supply current Idle mode supply current with all peripherals active Sleep and Power down mode supply current caused by 4) leakage Sleep ...
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I [mA] 140 120 100 Figure 4-1 Supply/Idle Current as a Function of Operating Frequency Data Sheet XC164GM Derivatives Electrical Parameters I DDImax I DDItyp I IDXmax I IDXtyp 40 f [MHz] ...
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I [mA] 3.0 2.0 1.0 4 Figure 4-2 Sleep and Power Down Supply Current due to RTC and Oscillator Running Function of Oscillator Frequency I PDL [mA] 1.5 1.0 0.5 -50 0 Figure 4-3 Sleep and Power Down ...
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Analog/Digital Converter Parameters Table 4-6 A/D Converter Characteristics (Operating Conditions apply) Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time for 10-bit 4) result Conversion time for 8-bit 4) result Calibration time ...
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V may exceed AIN AGND AREF cases will be X000 or X3FF H 3) The limit values for f must not be exceeded when selecting the peripheral frequency and the ADCTC setting This parameter ...
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Sample time and conversion time of the XC164GM’s A/D Converter are programmable. In compatibility mode, the above timing can be calculated using f The limit values for must not be exceeded when selecting ADCTC. BC Table 4-7 A/D Converter Computation ...
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AC Parameters 4.4.1 Definition of Internal Timing The internal operation of the XC164GM is controlled by the internal master clock The master clock signal different mechanisms. The duration of master clock periods (TCMs) and their variation (and also the ...
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The used mechanism to generate the master clock is selected by register PLLCON. CPU and EBC are clocked with the CPU clock signal f same frequency as the master clock ( f f two This factor is ...
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This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the ...
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Different frequency bands can be selected for the VCO, so the operation of the PLL can be adjusted to a wide range of input and output frequencies: Table 4-8 VCO Bands for PLL Operation PLLCON.PLLVB VCO Frequency Range 00 100 ...
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On-chip Flash Operation The XC164GM’s Flash module delivers data within a fixed access time (see Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles, where WS is the number of Flash access waitstates ...
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External Clock Drive XTAL1 Table 4-11 External Clock Drive Characteristics (Operating Conditions apply) Parameter Oscillator period 2) High time 2) Low time 2) Rise time 2) Fall time 1) The maximum limit is only relevant for PLL operation to ...
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Package and Reliability 5.1 Packaging Table 5-1 Package Parameters ( PG-TQFP-64-8 ) Parameter Power dissipation Thermal resistance Package Outlines 0.5 7.5 2) +0.07 0.2 -0. Index Marking 1) Does not include plastic or metal ...
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Flash Memory Parameters The data retention time of the XC164GM’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 5-2 ...
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Published by Infineon Technologies AG ...