SAF-XC164GM-8F20F INFINEON [Infineon Technologies AG], SAF-XC164GM-8F20F Datasheet - Page 60

• Manufacturer Part Number: SAF-XC164GM-8F20F
• Description: 16-Bit Single-Chip Microcontroller with C166SV2 Core
• Manufacturer: INFINEON [Infineon Technologies AG]

The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal f
same frequency as the master clock (
two:
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal
frequency as the CPU clock signal
Bypass Operation
When bypass operation is configured (PLLCTRL = 0x
the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:
f
If both divider factors are selected as ‘1’ (PLLIDIV = PLLODIV = ‘0’) the frequency of
directly follows the frequency of
cycle of the input clock
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
f
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (
the output divider (F = PLLMUL+1 / (PLLIDIV+1
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
is locked to
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because
f
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and
Data Sheet
MC
MC
MC
, the timing must be calculated using the minimum TCP possible under the respective
=
=
f
CPU
f
f
OSC
OSC
f
=
MC
/ ((PLLIDIV+1)
/ ((3 + 1)
f
f
MC
OSC
=
f
/ 2. This factor is selected by bit CPSYS in register SYSCON1.
OSC
. The slight variation causes a jitter of
F) which results from the input divider, the multiplication factor, and
(14 + 1)) =
f
OSC
(PLLODIV+1)).
.
f
OSC
f
OSC
f
CPU
so the high and low time of
Figure
/ 60.
f
CPU
.
58
=
4-6).
f
MC
) or can be the master clock divided by
B
) the on-chip phase locked loop is
B
f
CPU
MC
) the master clock is derived from
PLLODIV+1)). The PLL circuit
which also affects the duration
f
. The CPU clock can have the
MC
is constantly adjusted so it
f
f
MC
SYS
Electrical Parameters
is defined by the duty
which has the same
f
CPU
is derived from
Derivatives
V1.0, 2005-11
XC164GM
f
MC