ISL80102 INTERSIL [Intersil Corporation], ISL80102 Datasheet - Page 8

• Manufacturer Part Number: ISL80102
• Description: High Performance 2A and 3A LDOs
• Manufacturer: INTERSIL [Intersil Corporation]

Power-Good Operation
The PGOOD circuit monitors V
condition when V
voltage. The PGOOD flag is an open-drain NMOS that can
sink 10mA during a fault condition. The PGOOD pin
requires an external pull up resistor which is typically
connected to the VOUT pin. The PGOOD pin should not
be pulled up to a voltage source greater than V
a fault condition, the PGOOD output is pulled low. The
PGOOD fault can be caused by the current limit fault or
low input voltage. The PGOOD does not function during
thermal shutdown and when the part is disabled.
Output Voltage Selection
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage. This
voltage is then fed back to the error amplifier. The output
voltage can be programmed to any level between 0.8V
and 5V. An external resistor divider, R
set the output voltage as shown in Equation 1. The
recommended value for R
chosen according to Equation 2:
Power Dissipation
The junction temperature must not exceed the range
specified in the Recommended Operating Conditions. The
power dissipation can be calculated by using Equation 3:
V
R
P
OUT
1
D
=
=
R
(
=
V
2
IN
0.5V
×
⎛
⎝
–
V
--------------- - 1
0.5V
V
OUT
×
OUT
⎛
⎜
⎝
R
------ -
R
–
1
2
)
OUT
×
+
⎞
⎠
I
1
OUT
⎞
⎟
⎠
is below 84% of the nominal output
+
V
2
IN
8
is 500Ω to 1kΩ. R
×
I
OUT
GND
and signals a fault
1
and R
ISL80102, ISL80103
1
2
is then
, is used to
IN
. During
(EQ. 1)
(EQ. 2)
(EQ. 3)
The maximum allowed junction temperature, T
and the maximum expected ambient temperature,
T
temperature rise (ΔT
To calculate the maximum ambient operating
temperature, use the junction-to-ambient thermal
resistance (θ
Substitute P
operating temperature can be found by solving for T
using Equation 6:
Heatsinking The DFN Package
The DFN package uses the copper area on the PCB as a
heat-sink. The EPAD of this package must be soldered to
the copper plane (GND plane) for heat sinking. Figure 4
shows a curve for the θ
different copper area sizes.
ΔT
P
T
A(MAX)
FIGURE 4. 3mmx3mm-10 Pin DFN ON 4-LAYER PCB
A
D MAX
J
(
=
=
46
44
42
40
38
36
34
T
T
JMAX
2
)
J MAX
(
will determine the maximum allowed junction
=
(
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
4
T
–
D
WITH THERMAL VIAS θ
COPPER LAND AREA ON PCB
JA
J MAX
)
P
(
–
for P
D MAX
) for the DFN package with Equation 5:
T
6
(
A MAX
(
)
D(MAX)
–
8
)
T
×
J
A
) as shown in Equation 4:
)
θ
) θ
10
JA
JA
⁄
JA
of the DFN package for
and the maximum ambient
12
14
16
JA
vs EPAD-MOUNT
18
September 30, 2009
20
J(MAX)
22
2
(EQ. 4)
(EQ. 5)
(EQ. 6)
FN6660.0
24
A