HC5513_03 INTERSIL [Intersil Corporation], HC5513_03 Datasheet - Page 15

• Manufacturer Part Number: HC5513_03
• Description: TR909 DLC/FLC SLIC with Low Power Standby
• Manufacturer: INTERSIL [Intersil Corporation]

Notes
10. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal
11. Two-Wire Return Loss - The 2-wire return loss is computed
2. Overload Level (Two-Wire port) - The overload level is speci-
3. Longitudinal Impedance - The longitudinal impedance is
4. Longitudinal Current Limit (Off-Hook Active) - Off-Hook
5. Longitudinal Current Limit (On-Hook Standby) - On-Hook
6. Longitudinal to Metallic Balance - The longitudinal to metal-
7. Metallic to Longitudinal FCC Part 68, Para 68.310 - The
8. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire
9. Metallic to Longitudinal Balance - The metallic to longitudinal
fied at the 2-wire port (V
receive port (E
E
computed using the following equations, where TIP and RING
voltages are referenced to ground. L
A
(TIP) L
(RING) L
Where: E
(Active, C
by increasing the amplitude of E
longitudinal balance drops below 45dB. DET pin remains low
(no false detection).
(Active, C
increasing the amplitude of E
dinal balance drops below 45dB. DET pin remains high (no false
detection).
lic balance is computed using the following equation:
BLME = 20 • log (E
Figure 4.
metallic to longitudinal balance is defined in this spec.
balance is computed using the following equation:
BLFE = 20 • log (E
balance is computed using the following equation:
BMLE = 20 • log (E
Where: E
balance is computed using the following equation:
BFLE = 20 • log (E
Where: E
using the following equation:
r = -20 • log (2V
E0
1
1
1
1
1
1
1
1
T
RX
are defined in Figure 2.
until 1% THD is measured at V
ZT
ZR
L
1
TR
RX
1
= V
= 1V
= 1, C
= 1, C
E1
, V
= V
, V
0
0
0
0
1
1
1
1
T
/A
RX
L
L
R
RMS
M
T
and E
and E
2
/A
). I
/V
2
= 1) longitudinal current limit is determined by
L
RX
TR
R
= 0) longitudinal current limit is determined
L
/V
S
DCMET
(0Hz to 100Hz).
/V
)
/V
/V
TX
RX
TR
C1
TR0
TR
L
0
0
1
1
0
0
1
1
L
),: E
), E
), E
are defined in Figure 5.
are defined in Figure 5.
), where: E
) with the signal source at the 4-wire
15
L
= 30µA, increase the amplitude of
TR
L
RX
(Figure 3B) until the 2-wire longitu-
and V
= source is removed.
= 0
L
TRO
C2
(Figure 3A) until the 2-wire
0
1
0
1
0
1
0
1
TX
ZT
L
. Reference Figure 1.
, L
and V
are defined in Figure 4.
ZR
Open Circuit
Active
Ringing
Standby
Open Circuit
Active
Ringing
Standby
SLIC OPERATING STATE
, V
TR
T
are defined in
, V
TABLE 1. LOGIC TRUTH TABLE
R
, A
R
and
HC5513
12. Overload Level (4-Wire port) - The overload level is specified
13. Output Offset Voltage - The output offset voltage is specified
No Active Detector
Ground Key Detector
No Active Detector
Ground Key Detector
No Active Detector
Loop Current Detector
Ring Trip Detector
Loop Current Detector
Where: Z
impedance of the line, nominally 600Ω. (Reference Figure 6).
at the 4-wire transmit port (V
the 2-wire port, I
7). Increase the amplitude of E
V
is equal to 1.
with the following conditions: E
and is measured at V
in Figure 7. Note: I
resistor between tip and ring.
TXO
ACTIVE DETECTOR
. Note that the gain from the 2-wire port to the 4-wire port
D
= The desired impedance; e.g., the characteristic
DCMET
DCMET
TX
= 23mA, Z
. E
G
is established with a series 600Ω
TXO
, I
G
DCMET
G
) with the signal source (E
= 0, I
until 1% THD is measured at
L
= 20kΩ (Reference Figure
, V
DCMET
Logic Level High
TX
DET OUTPUT
and Z
= 23mA, Z
L
are defined
L
G
=
) at
∞