EL5226 INTERSIL [Intersil Corporation], EL5226 Datasheet - Page 7

• Manufacturer Part Number: EL5226
• Description: 10- and 12-Channel TFT-LCD Reference Voltage Generators
• Manufacturer: INTERSIL [Intersil Corporation]

General Description
The EL5226 and EL5326 provide a versatile method of
providing the reference voltages that are used in setting the
transfer characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5226
and EL5326, the V/T curve can be changed to optimize its
characteristics according to the required application of the
display product. Each of the eight reference voltage outputs
can be set with a 10-bit resolution. These outputs can be
driven to within 50mV of the power rails of the EL5226 and
EL5326. As all of the output buffers are identical, it is also
possible to use the EL5226 and EL5326 for applications
other than LCDs where multiple voltage references are
required that can be set to 10 bit accuracy.
Digital Interface
The EL5226 and EL5326 use a simple two-wire I
interface to program the outputs. The bus line SCLK is the
clock signal line and bus SDA is the data information signal
line. The EL5226 and EL5326 can support the clock rate up
to 400kHz. External pull up resistor is required for each bus
line. The typical value for these two pull up resistor is about
1kΩ.
START AND STOP CONDITION
The Start condition is a high to low transition on the SDA line
while SCLK is high. The Stop condition is a low to high
transition on the SDA line while SCLK is high. The start and
stop conditions are always generated by the master. The
bus is considered to be busy after the start condition and to
be free again a certain time after the stop condition. The two
bus lines must be high when the buses are not in use. The
I
DATA VALIDITY
The data on the SDA line must be stable during the high
period of the clock. The high or low state of the data line can
only change when the clock signal on the SCLK line is low.
BYTE FORMAT AND ACKNOWLEDGE
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
The master puts a resistive high level on the SDA line during
the acknowledge clock pulse. The peripheral that
acknowledges has to pull down the SDA line during the
acknowledge clock pulse.
DEVICES ADDRESS AND W/R BIT
Data transfers follow the format shown in Timing Diagram 1.
After the Start condition, a first byte is sent which contains
2
C Timing Diagram 2 shows the format.
7
2
C digital
EL5226, EL5326
the Device Address and write/read bit. This address is a 7-
bit long device address and only two device addresses (74H
and 75H) are allowed for the EL5226 and EL5326. The first
6 bits (A6 to A1, MSBs) of the device address have been
factory programmed and are always 111010. Only the least
significant bit A0 is allowed to change the logic state, which
can be tied to V
and EL5326 may be used on the same bus at one time. The
EL5226 and EL5326 monitor the bus continuously and
waiting for the start condition followed by the device address.
When a device recognizes its device address, it will start to
accept data. An eighth bit is followed by the device address,
which is a data direction bit (W/R). A "0" indicates a Write
transmission and a "1" indicates a Read transmission.
The EL5226 and EL5326 can be operated as Standard
mode and Register mode. See the I
detail formats.
STANDARD MODE
The part operates at Standard Mode if pin 1 (STD/REG) is
held high. The Standard Mode allows the user to program all
outputs at one time. Two data bytes are required for 10-bit
data for each channel output and there are a total of 20/24
data bytes for 10/12 channels. Data in data byte 1 and 2 is
for channel A. Data in data byte 15 and 16 is for channel H.
D9 to D0 are the 10-bit data for each channel. The unused
bits in the data byte are "don't care" and can be set to either
one or zero. See Table 1 for program sample for one
channel setting:
When the W/R bit is high, the master can read the data from
the EL5226 and EL5326. See Timing Diagram 1 for detail
formats.
REGISTER MODE
The part operates at Register Mode if pin 1 (STD/REG) is
held low. The Register Mode allows the user to program
each output individually. Followed by the first byte, the
second byte sets the register address for the programmed
output channel. Bits R0 to R3 set the output channel
address. For the unused bits in the R4 to R7 are "don't care".
See Table 2 for program sample.
The EL5226 and EL5326 also allows the user to read the
data at Register Mode. See Timing Diagram 1 for detail
formats.
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
SD
DATA
0
0
0
1
or DGND. A maximum of two EL5226
0
0
1
1
TABLE 1.
0
0
1
1
0
0
1
1
0
0
1
1
2
C Timing Diagram 1 for
0 Data value = 0
0 Data value = 512
1 Data value = 31
1 Data value = 1023
CONDITION