EL5156 INTERSIL [Intersil Corporation], EL5156 Datasheet - Page 11

• Manufacturer Part Number: EL5156
• Manufacturer: INTERSIL [Intersil Corporation]

determine if load conditions or package types need to be
modified to assure operation of the amplifier in a safe
operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 2:
Where:
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
For sourcing:
For sinking:
Where:
PD
PD
PD
T
T
θ
V
I
V
R
I
N = number of amplifiers (max = 2)
SMAX
LOAD
MAX
MAX
MAX
AMAX
JA
JMAX
S
OUT
LOAD
= Supply voltage
= Thermal resistance of the package
=
=
=
= Maximum output voltage of the application
= Load current
= Maximum quiescent supply current
= Maximum junction temperature
= Maximum ambient temperature
= Load resistance tied to ground
V
V
T
-------------------------------------------- -
S
JMAX
S
×
×
I
I
SMAX
SMAX
Θ
–
JA
T
AMAX
+
+
i
i
∑
∑
=
=
n
n
1
1
(
(
V
V
11
OUTi
S
–
V
OUTi
–
V
S
)
)
×
×
EL5156, EL5157, EL5256, EL5257
I
V
---------------- -
LOADi
OUTi
R
Li
(EQ. 4)
(EQ. 2)
(EQ. 3)
By setting the two PD
can solve the output current and R
overheat.
Power Supply Bypassing Printed Circuit Board
Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the V
supply rail. See Figure 37 for a complete tuned power supply
bypass methodology.
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
MAX
equations equal to each other, we
S
- pin becomes the negative
LOAD
to avoid the device
September 13, 2007
FN7386.5