X98027L128-3.3 INTERSIL [Intersil Corporation], X98027L128-3.3 Datasheet
X98027L128-3.3
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X98027L128-3.3 Summary of contents
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Data Sheet 275MHz Triple Video Digitizer with Digital PLL The X98027 3-channel, 8-bit Analog Front End (AFE) contains all the components necessary to digitize analog RGB or YUV graphics signals from personal computers, workstations and video set-top boxes. The ...
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... Ordering Information PART NUMBER X98027L128-3.3 X98027L128-3.3-Z (See Note) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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Absolute Maximum Ratings Voltage (referenced to GND =GND =GND ) . . . . . . . . . . . . . . . . . . . 4.0V ...
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Electrical Specifications Specifications apply for V unless otherwise noted (Continued) SYMBOL PARAMETER DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINV V Input HIGH Voltage IH V Input LOW Voltage IL I Input leakage current Input capacitance SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNC ...
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Electrical Specifications Specifications apply for V unless otherwise noted (Continued) SYMBOL PARAMETER t DATA valid after rising edge of DATACLK HOLD AC TIMING CHARACTERISTICS (2 WIRE INTERFACE) f SCL Clock Frequency SCL Maximum width of a glitch on SCL that ...
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HSYNC IN Analog P P Video DATACLK [7: [7: OUT Th HSYNC d The HSYNC edge (programmable leading or trailing) that the DPLL is ...
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The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. HSYNC IN The sampling phase setting determines its relative position to the rest of the AFE’s output signals t HSYNCin-to-HSout Analog ...
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Pinout 8 X98027 X98027 (128-PIN MQFP) TOP VIEW FN8221.0 May 26, 2005 ...
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Pin Descriptions SYMBOL PIN Analog input. Red channel 1. DC couple or AC couple through 0.1µ Analog input. Green channel 1. DC couple or AC couple through 0.1µ Analog ...
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Pin Descriptions (Continued) SYMBOL PIN HS 125 3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. OUT This output is always purely horizontal sync (without any composite sync signals) VS 126 ...
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Register Listing ADDRESS REGISTER (DEFAULT VALUE) 0x01 SYNC Status (read only) 0x02 SYNC Polarity (read only) 0x03 HSYNC Slicer (0x44) 0x04 SOG Slicer (0x08) 11 X98027 BIT(s) FUNCTION NAME 0 HSYNC1 Active 0: HSYNC1 is Inactive 1: HSYNC1 is Active ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x05 Input configuration (0x00) 0x06 Red Gain (0x55) 0x07 Green Gain (0x55) 0x08 Blue Gain (0x55) 0x09 Red Offset (0x80) 0x0A Green Offset (0x80) 0x0B Blue Offset (0x80) 0x0C Offset DAC Configuration (0x00) ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x0D AFE Bandwidth (0x0E) 0x0E PLL Htotal MSB (0x03) 0x0F PLL Htotal LSB (0x20) 0x10 PLL Sampling Phase (0x00) 0x11 PLL Pre-coast (0x08) 0x12 PLL Post-coast (0x00) 0x13 PLL Misc (0x00) 0x14 DC ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x17 ABLC™ Configuration (0x40) 0x18 Output Format (0x00) 0x19 HSOUT Width (0x10) 0x1A Output Signal Disable (0x00) 14 X98027 BIT(s) FUNCTION NAME 0 ABLC™ disable 0: ABLC™ enabled (default) 1: ABLC™ disabled 1 ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x1B Power Control (0x00) 0x1C Reserved (0x47) 0x23 DC Restore Clamp (0x08) 0x2B Crystal Compensation (0x14) Technical Highlights The X98027 provides all the features of traditional triple channel video AFEs, but adds several ...
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Offset can drift significantly over 50°C, reducing image quality and requiring that the user do ...
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Input Coupling Inputs can be either AC-coupled (default) or DC-coupled (see register 0x05[1]). AC coupling is usually preferred since it allows video signals with substantial DC offsets to be accurately digitized. The X98027 provides a complete internal DC-restore function, including ...
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ACTIVITY 0x01[6:0] & POLARITY 0x02[5:0] DETECT HSYNC1 HSYNC 1 SLICER IN 0x03[2:0] VSYNC 1 IN SOG SLICER SOG 1 IN 0x1C HSYNC2 HSYNC 2 SLICER IN 0x03[6:4] VSYNC 2 IN SOG SLICER SOG 2 IN 0x1C CLOCKINV IN XTAL IN ...
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Table 3 shows the corner frequency for different register settings. TABLE 3. BANDWIDTH CONTROL 0x0D[3:0] VALUE (LSB = “x” = “don’t care”) AFE BANDWIDTH 000x 001x 010x 011x 100x 101x 110x 111x Register 0x0D[7:4] controls a programmable zero, allowing high ...
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TABLE 5. OFFSET DAC RANGE AND OFFSET DAC ADJUSTMENT OFFSET DAC 10 BIT RANGE OFFSET DAC 0x0C[0] RESOLUTION 0 0.25 ADC LSBs (0.68mV) 1 0.125 ADC LSBs (0.34mV) 0 0.25 ADC LSBs (0.68mV) 1 0.125 ADC LSBs (0.34mV) Clock Generation ...
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HSYNC VSYNC SOG DETECT DETECT DETECT HSYNC and VSYNC Activity Detect Activity on these bits always indicates valid sync pulses, so they should have the ...
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HSYNC OUT HSYNC is an unmodified, buffered version of the OUT incoming HSYNC or SOG signal of the selected IN IN channel, with the incoming signal’s period, polarity, and width to aid in mode detection. HSYNC format as the incoming ...
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HSYNC DPLL Lock Edge IN (to A and B) Analog Video (to A and B) N-3 N-2 N-1 N DATACLK (A) DATA (A) HS (A) OUT DATACLK (B) DATA (B) HS (B) OUT Crystal Oscillator ...
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HSYNC DPLL Lock Edge IN (to A and B) Analog Video N-3 N-2 N-1 N (to A and B) PIXELCLK (A) (Internal) DATACLK (A) DATA (A) PRI DATA (A) SEC HS (A) OUT PIXELCLK ...
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TABLE 8. X98027 CRYSTAL COMPENSATION REGISTER 0x2B VALUE CRYSTAL FREQUENCY VALUE RANGE (MHz) (DECIMAL 23 25.0 - 26 Conditions required: negative polarity VSYNC, with no serrations, and t ...
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Communication is accomplished in three steps: 1. The Host selects the X98027 it wishes to communicate with. 2. The Host writes the initial X98027 Configuration Register address it wishes to write to or read from. 3. The Host writes to ...
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SCL SDA FIGURE 14. VALID DATA CHANGES ON THE SDA BUS START Command X98027 Serial Bus Address (Repeat if desired) STOP Command S T Serial ...
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START Command X98027 Serial Bus Address START Command X98027 Serial Bus Address (Repeat if desired) STOP Command S T Serial ...
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Metric Quad Flat Pack (MQFP) Package Type L All dimensions in mm. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by ...