X28HC256DI-12 INTERSIL [Intersil Corporation], X28HC256DI-12 Datasheet
X28HC256DI-12
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X28HC256DI-12 Summary of contents
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... PP The X28HC256 supports a 128-byte page write opera- tion, effectively providing a 24µs/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 ...
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... X28HC256KMB-15 X28HC256KMB-15 X28HC256P-15 X28HC256P-15 X28HC256PZ-15 (Note) X28HC256P-15 Z X28HC256PI-15 X28HC256PI-15 X28HC256PIZ-15 (Note) X28HC256PI-15 Z X28HC256PM-15 X28HC256PM-15 X28HC256SI-15* X28HC256SI-15 X28HC256SM-15 X28HC256SM-15 X28HC256D-12 X28HC256D-12 X28HC256DI-12 X28HC256DI-12 X28HC256DM-12 X28HC256DM-12 X28HC256DMB-12 X28HC256DMB-12 X28HC256EI-12 X28HC256EI-12 X28HC256EM-12 X28HC256EM-12 X28HC256EMB-12 X28HC256EMB-12 X28HC256FMB-12 X28HC256FMB-12 X28HC256J-12* X28HC256J-12 X28HC256JZ-12* (Note) X28HC256J-12 Z X28HC256JI-12* X28HC256JI-12 ...
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... Ordering Information (Continued) PART NUMBER PART MARKING X28HC256S-12* X28HC256S-12 X28HC256SZ-12 (Note) X28HC256S-12 Z X28HC256SI-12* X28HC256SI-12 X28HC256SIZ-12 (Note) X28HC256SI-12 Z X28HC256SM-12* X28HC256SM-12 X28HC256D-90 X28HC256D-90 X28HC256DI-90 X28HC256DI-90 X28HC256DM-90 X28HC256DM-90 X28HC256DMB-90 X28HC256DMB-90 X28HC256EM-90 X28HC256EM-90 X28HC256EMB-90 X28HC256EMB-90 X28HC256FI-90 X28HC256FI-90 X28HC256FM-90 X28HC256FM-90 X28HC256FMB-90 X28HC256FMB-90 X28HC256J-90* X28HC256J-90 X28HC256JZ-90* (Note) ...
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... PIN DESCRIPTIONS Addresses ( The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power con- sumption is reduced. Output Enable (OE) The Output Enable input controls the data output buff- ers, and is used to initiate read operations ...
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... Page Write Operation The page write feature of the X28HC256 allows the entire memory to be written in typically 0.8 seconds. Page write allows up to one hundred twenty-eight bytes of data to be consecutively written to the X28HC256, prior to the commencement of the internal programming cycle ...
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DATA POLLING I/O 7 Figure 2. DATA Polling Bus Sequence Last Write HIGH Z I – Figure 3. DATA Polling Software Flow Write Data Writes Complete? Yes Save Last ...
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THE TOGGLE BIT I/O 6 Figure 4. Toggle Bit Bus Sequence Last Write I Figure 5. Toggle Bit Software Flow ¬ Last Write Yes Load Accum From Addr n Compare Accum with Addr n ...
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SOFTWARE ALGORITHM Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. SOFTWARE DATA PROTECTION ...
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... SYSTEM CONSIDERATIONS Because the X28HC256 is frequently used in large memory arrays provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipa- tion, and eliminate the possibility of contention where multiple I/O pins share the same bus ...
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ABSOLUTE MAXIMUM RATINGS Temperature under bias X28HC256 ....................................... -10°C to +85°C X28HC256I, X28HC256M .............. -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to V ........................................ -1V to +7V SS D.C. output current ............................................. ...
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CAPACITANCE T = +25° 1MHz Symbol (9) C Input/output capacitance I/O (9) C Input capacitance IN ENDURANCE AND DATA RETENTION Parameter Endurance Data retention A.C. CONDITIONS OF TEST Input pulse levels Input rise and fall times ...
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A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits Symbol Parameter (5) t Read cycle time RC (5) t Chip enable access time CE (5) t Address access time AA t Output enable access time OE ...
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Write Cycle Limits Symbol Parameter (7) t Write cycle time WC t Address setup time AS t Address hold time AH t Write setup time CS t Write hold time pulse width HIGH setup ...
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... Notes: (9) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. ...
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DATA Polling Timing Diagram Address OEH I (11) Toggle Bit Timing Diagram OEH OE HIGH Z I I/O 6 Note: (11)Polling operations ...