X28HC64DI-12 INTERSIL [Intersil Corporation], X28HC64DI-12 Datasheet

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X28HC64DI-12

Manufacturer Part Number
X28HC64DI-12
Description
5 Volt, Byte Alterable EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet

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5 Volt, Byte Alterable EEPROM
FEATURES
• 70ns access time
• Simple byte and page write
• Low power CMOS
• Fast write cycle times
• Software data protection
• End of write detection
PIN CONFIGURATIONS
V
A
I/O
I/O
I/O
NC
—Single 5V supply
—No external high voltages or V
—Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
—40mA active current max.
—200µA standby current max.
—64-byte page write operation
—Byte or page write cycle: 2ms typical
—Complete memory rewrite: 0.25 sec. typical
—Effective byte write cycle time: 32µs typical
—DATA polling
—Toggle bit
SS
A
A
A
A
A
A
A
A
12
7
6
5
4
3
2
1
0
0
1
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Plastic DIP
X28HC64
Flat Pack
CERDIP
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
WE
NC
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
8
9
11
10
7
6
5
4
3
®
1
I/O
NC
A
A
A
A
A
A
A
6
5
4
3
2
1
0
0
Data Sheet
13
5
6
7
8
9
10
11
12
14 15 16 17 18 19 20
4
PP
3
(Top View)
control circuits
X28HC64
2
PLCC
LCC
1 32 31 30
1-888-INTERSIL or 1-888-468-3774
29
28
27
26
25
24
23
22
21
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
A
A
A
NC
OE
A
CE
I/O
I/O
8
9
11
10
7
6
I/O 0
I/O 1
I/O 2
V SS
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A 10
NC
NC
CE
A 2
A 1
A 0
• High reliability
• JEDEC approved byte-wide pin out
DESCRIPTION
The X28HC64 is an 8K x 8 EEPROM, fabricated with
Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable non-
volatile memories, the X28HC64 is a 5V only device. It
features the JEDEC approved pinto for byte-wide mem-
ories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle, and
enabling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Intersil’s hardware write protect capability.
Intersil EEPROMs are designed and tested for appli-
cations requiring extended endurance. Inherent data
retention is greater than 100 years.
—Endurance: 1 million cycles
—Data retention: 100 years
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
All other trademarks mentioned are the property of their respective owners.
June 1, 2005
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
12
11
9
7
5
4
I/O
I/O
A
A
A
A
1
3
5
6
1
0
13
10
8
6
2
3
Copyright Intersil Americas Inc. 2005. All Rights Reserved
I/O
A
A
A
A
A
Bottom View
0
2
4
12
7
2
(BOTTOM
X28HC64
X28HC64
VIEW)
TSOP
PGA
15
14
28
1
I/O
V
V
NC
SS
CC
3
17
16
20
22
24
27
OE
I/O
I/O
CE
A
WE
9
5
4
18
19
21
23
25
26
I/O
I/O
A
A
A
NC
10
11
8
6
7
64K, 8K x 8 Bit
X28HC64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FN8109.0
A 3
A 4
A 5
A 6
A 7
A 12
NC
NC
V CC
NC
WE
NC
A 8
A 9
A 11
OE

Related parts for X28HC64DI-12

X28HC64DI-12 Summary of contents

Page 1

... RAMs. The X28HC64 supports a 64-byte page write operation, effectively providing a 32µs/byte write cycle, and enabling the entire memory to be typically written in 0.25 seconds. The X28HC64 also features DATA Polling and Toggle Bit Polling, two methods providing early end of write detection ...

Page 2

... PIN DESCRIPTIONS Addresses ( The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power con- sumption is reduced. Output Enable (OE) The Output Enable input controls the data output buff- ers and is used to initiate read operations ...

Page 3

... Page Write Operation The page write feature of the X28HC64 allows the entire memory to be written in 0.25 seconds. Page write allows two to sixty-four bytes of data to be consecu- tively written to the X28HC64 prior to the commence- ment of the internal programming cycle. The host can ...

Page 4

DATA POLLING I/O 7 Figure 2. DATA Polling Bus Sequence Last Write HIGH Z I – Figure 3. DATA Polling Software Flow Write Data Writes Complete? Yes Save Last ...

Page 5

THE TOGGLE BIT I/O 6 Figure 4. Toggle Bit Bus Sequence Last WE Write Beginning and ending state of I/O Figure 5. Toggle Bit Software Flow Last Write Yes Load Accum From Addr N ...

Page 6

HARDWARE DATA PROTECTION The X28HC64 provides two hardware features that protect nonvolatile data from inadvertent writes. – Default V Sense—All write functions are inhibited CC when typically. CC – Write Inhibit—Holding either OE LOW, WE HIGH, or ...

Page 7

SOFTWARE DATA PROTECTION Figure 6. Timing Sequence—Byte or Page Write Data AAA ADDR 1555 CE WE Figure 7. Write Sequence for Software Data Protection Write Data AA to Address 1555 Write Data 55 to Address 0AAA Write ...

Page 8

RESETTING SOFTWARE DATA PROTECTION Figure 8. Reset Software Data Protection Timing Sequence V CC AAA Data 1555 0AAA ADDR CE WE Figure 9. Software Sequence to Deactivate Software Data Protection Write Data AA to Address 1555 Write Data 55 to ...

Page 9

... SYSTEM CONSIDERATIONS Because the X28HC64 is frequently used in large memory arrays provided with a two-line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipa- tion, and eliminate the possibility of contention where multiple I/O pins share the same bus. ...

Page 10

ABSOLUTE MAXIMUM RATINGS Temperature under bias X28HC64 ......................................... -10°C to +85°C X28HC64I, X28HC64M .................. -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to V ......................................... -1V to +7V SS D.C. output current ............................................... ...

Page 11

ENDURANCE AND DATA RETENTION Parameter Minimum endurance Data retention POWER-UP TIMING Symbol (3) t Power-up to read operation PUR (3) t Power-up to write operation PUW CAPACITANCE T = +25° 1MHz Symbol Parameter (3) C Input/output ...

Page 12

A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read Cycle Limits Symbol Parameter t Read cycle time RC t Chip enable access time CE t Address access time AA t Output enable access time OE ( ...

Page 13

WRITE CYCLE LIMITS Symbol Parameter (5) t Write cycle time WC t Address setup time AS t Address hold time AH t Write setup time CS t Write hold time pulse width High setup ...

Page 14

... Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. ...

Page 15

DATA Polling Timing Diagram Address OEH I (9) Toggle Bit Timing Diagram OEH OE HIGH Z I/ I/O 6 Note: (9) Polling ...

Page 16

Ordering Information X28HC64 Device All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make ...

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