HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet - Page 8

• Manufacturer Part Number: HYB18T512400BF-2.5
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

2
This chapter contains the chip configuration and addressing.
2.1
The chip configuration of a DDR2 SDRAM is listed by function in
columns are explained in
for ×4,
Rev. 1.1, 2007-05
03292006-YBYM-WG0Z
Ball#
Clock Signals ×4/×8 organization
E8
F8
F2
Clock Signals ×16 organization
J8
K8
K2
Control Signals ×4/×8 organizations
F7
G7
F3
G8
Control Signals ×16 organization
K7
L7
K3
L8
Address Signals ×4/×8 organizations
G2
G3
Figure 2
for ×8 and
Name
CK
CK
CKE
CK
CK
CKE
RAS
CAS
WE
CS
RAS
CAS
WE
CS
BA0
BA1
Chip Configuration
Chip Configuration
Table 8
Figure 3
Ball
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
and
for ×16.
Table 9
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
respectively. The ball numbering for the FBGA package is depicted in
Function
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
Clock Signal CK, Complementary Clock Signal CK
Note: See functional description in x4/x8 organization
Clock Enable
Note: See functional description in x4/x8 organization
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Bank Address Bus 1:0
8
Table
7. The abbreviations used in the Ball# and Buffer Type
512-Mbit Double-Data-Rate-Two SDRAM
Chip Configuration of DDR2 SDRAM
HYB18T512[40/80/16]0B[C/F]
Internet Data Sheet
TABLE 7
Figure 1