HYB18T512800B2F QIMONDA [Qimonda AG], HYB18T512800B2F Datasheet - Page 28

• Manufacturer Part Number: HYB18T512800B2F
• Description: 200-Pin SO-DIMM DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

3.4
List of tables defining
•
•
•
•
•
•
•
Rev. 1.1, 2007-01
08212006-PKYN-2H1B
Parameter
Operating Current 0
One bank Active - Precharge;
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge;
t
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Data bus inputs are FLOATING.
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Active Power-Down Current
All banks open;
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open;
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
bus inputs are SWITCHING;
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
RCD
RAS
RP
RAS
Table 20 “I
Table 21 “Definitions for I
Table 22 “I
Table 23 “I
Table 24 “I
Table 25 “I
Table 26 “I
=
=
=
=
t
RPMIN
t
t
t
RAS.MAX
RAS.MAX.
RCD.MIN
; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
DD
DD
DD
DD
DD
DD
, AL = 0, CL = CL
,
,
t
t
t
t
RP
CK
CK
Specification for HYS64T[32/64/128]xxxEDL–2.5–B2” on Page 31
Specification for HYS64T[32/64/128]xxxEDL–3S–B2” on Page 33
RP
Measurement Conditions” on Page 28
Specification for HYS64T[32/64/128]xxxEDL–25F–B2” on Page 30
Specification for HYS64T[32/64/128]xxxEDL–3–B2” on Page 32
Specification for HYS64T[32/64/128]xxxEDL–3.7–B2” on Page 34
=
=
=
=
I
t
t
t
I
t
RP.MIN
CK.MIN
CK.MIN
DD
RP.MAX
DD
Specifications and Conditions.
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
Specifications and Conditions
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
I
t
DD
OUT
CK
MIN
” on Page 29
=
= 0mA.
; CKE is HIGH, CS is HIGH between valid commands. Address and
t
CK.MIN
I
OUT
t
,
CK
t
t
= 0 mA, BL = 4,
RC
CK
=
=
=
t
CK.MIN
t
t
RC.MIN
CK.MIN
I
OUT
; Other control and address inputs are SWITCHING,
,
; Other control and address inputs are STABLE,
= 0 mA.
t
RAS
=
t
CK
t
28
RAS.MIN
=
t
MIN
CK.MIN
MIN
, CKE is HIGH, CS is HIGH between
;
;
t
t
CK
CK
,
t
RC
=
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
=
t
t
CKMIN
=
CK.MIN
t
MIN
RC.MIN
;
Small Outlined DDR2 SDRAM Modules
;
;
t
t
RAS
CK
,
t
=
RAS
=
t
CK.MIN
t
RASMAX
=
I
DD
t
RAS.MIN
;
Measurement Conditions
;
,
Internet Data Sheet
Symbol Note
I
I
I
I
I
I
I
I
I
I
DD0
DD1
DD2N
DD2P
DD2Q
DD3N
DD3P(0)
DD3P(1)
DD4R
DD4W
TABLE 20
1)2)3)4)5)
—
6)
—
—
—
—
—
—
6)
—