EL7586 INTERSIL [Intersil Corporation], EL7586 Datasheet - Page 16

• Manufacturer Part Number: EL7586
• Description: TFT-LCD Power Supply
• Manufacturer: INTERSIL [Intersil Corporation]

Charge Pump Output Capacitors
Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by the following equation:
C
where f
Start-Up Sequence
Figure 33 and 34 show a detailed start-up sequence
waveform. For a successful power up, there should be six
peaks at V
latch off until either EN is toggled or the input supply is
recycled.
When the input voltage is higher than 2.5V, an internal
current source starts to charge C
using a fast ramp followed by a slow ramp. During the initial
slow ramp, the device checks whether there is a fault
condition. If no fault is found, C
first peak and V
During the second ramp, the device checks the status of
V
ramp, PG output goes low and enables the input protection
PMOS Q1. Q1 is a controlled FET used to prevent in-rush
current into V
Its rate of turn on is controlled by C
detected, M1 will turn off and disconnect the inductor from
V
With the input protection FET on, NODE1 (See Typical
Application Diagram) will rise to ~V
not enabled so V
output diode. Hence, there is a step at V
part of the start-up sequence. If this step is not desirable, an
external PMOS FET can be used to delay the output until the
boost is enabled internally. The delayed output appears at
A
For the EL7586, V
beginning of the third ramp. The soft-start ramp depends on
the value of the C
soft-start time is ~2ms.
The EL7586A is the same as the EL7586 except V
V
When a fault is detected, the outputs and the input protection
will turn off but V
V
peak, DELB gate goes low to turn on the external PMOS Q4
to generate a delayed V
V
PG, V
VDD
OUT
REF
IN
LOGIC
OFF
ON
.
is enabled at the beginning of the sixth ramp. A
.
OFF
≥
and over temperature. At the peak of the second
turns on at the start of the fourth peak. At the fifth
OSC
------------------------------------------------------
2
turn on when input voltage (V
×
, DELB and V
CDLY
V
RIPPLE
is the switching frequency.
BOOST
I
OUT
. When a fault is detected, the device will
REF
REF
BOOST
DLY
BOOST
×
turns on.
before V
f
will stay on.
OSC
capacitor. For C
ON
BOOST
rises to V
and V
are checked at end of this ramp.
16
BOOST
CDLY
output.
LOGIC
CDLY
IN
o
IN
. When a fault is
-V
is discharged after the
. Initially the boost is
is enabled internally.
DD
DLY
DIODE
to an upper threshold
soft-start at the
BOOST
) exceeds 2.5V.
of 220nF, the
through the
during this
REF
VDD
EL7586, EL7586A
and
,
Fault Protection
Once the start-up sequence is complete, the voltage on the
C
detected or the EN pin is disabled. If a fault is detected, the
voltage on C
disabled until the power is recycled or enable is toggled.
Component Selection for Start-Up Sequencing and
Fault Protection
The C
to stabilize the V
22nF to 1µF and should not be more than five times the
capacitor on C
The C
range from 47nF minimum to several microfarads - only
limited by the leakage in the capacitor reaching µA levels.
C
above). Note with 220nF on C
typically 50ms and the use of a larger/smaller value will vary
this time proportionally (e.g. 1µF will give a fault time-out
period of typically 230ms).
Fault Sequencing
The EL7586 and EL7586A have advanced fault detection
systems which protects the IC from both adjacent pin shorts
during operation and shorts on the output supplies.
A high quality layout/design of the PCB, in respect of
grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme - especially
during start-up. The user is directed to the layout guidelines
and component selection sections to avoid problems during
initial evaluation and prototype PCB generation.
DLY
DEL
capacitor remains at 1.15V until either a fault is
REF
DEL
should be at least 1/5 of the value of C
capacitor is typically 220nF and has a usable
capacitor is typically set at 220nF and is required
DLY
DEL
REF
rises to 2.4V at which point the chip is
to ensure correct start-up operation.
output. The range of C
DEL
the fault time-out will be
REF
REF
is from
October 7, 2005
(See
FN9210.1