LT3837EFE-PBF LINER [Linear Technology], LT3837EFE-PBF Datasheet - Page 19

• Manufacturer Part Number: LT3837EFE-PBF
• Description: Isolated No-Opto Synchronous Flyback Controller
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of
the primary side MOSFET. Correct setting eliminates
overlap between the primary side switch and secondary
side synchronous switch(es) and the subsequent current
spike in the transformer. This spike will cause additional
component stress and a loss in regulator effi ciency.
The primary gate delay resistor is set with the following
equation:
A good starting point is 27k.
Soft-Start Functions
The LT3837 contains an optional soft-start function that is
enabled by connecting an external capacitor between the
SFST pin and ground. Internal circuitry prevents the control
voltage at the V
There is an initial pull-up circuit to quickly bring the SFST
voltage to approximately 0.8V. From there it charges to
approximately 2.8V with a 20μA current source.
The SFST node is then discharged to 0.8V when a fault
occurs. A fault is V
current sense voltage greater than 200mV or the IC’s
thermal (overtemperature) shutdown is tripped. When
SFST discharges, the V
to below the minimum current voltage. Once discharged,
the SFST recharges up again.
In this manner, switch currents are reduced and the stresses
in the converter are reduced during fault conditions.
The time it takes to fully charge soft-start is:
R
t
SS
PGDLY
=
C
SFST
(
k
20
Ω =
)
C
μ
• .
pin from exceeding that on the SFST pin.
1 4
A
t
PGDLY
V
CC
=
C
too low (undervoltage lockout),
9 01
70
( )
.
node voltage is also pulled low
ns
ms C
+ 47
•
SFST
( )
μ
F
Referring to Figure 4, the voltage hysteresis at V
equal to the change in bias current times R
procedure is to select the desired V
hysteresis, V
where:
R
UVLO Pin Function
The UVLO pin provides a user programming undervoltage
lockout. This is usually used to provide undervoltage
lockout based on V
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
V
(3a) UV Turning ON
B
IN
R
R
I
R
R
UVLO
is then selected with the desired turn-on voltage:
A
B
B
A
=
=
UVLO
⎛
⎜
⎝
= I
V
LT3837
I
UVHYS
V
UVLO
V
UVLOL
IN ON
UVLO
I
UVLO
UVHYS
(
R
A
)
– I
– 1
IN
. Then:
(3b) UV Turning OFF
V
UVLOH
⎞
⎟
⎠
. The gate drivers are disabled when
IN
R
R
A
B
Figure 4
UVLO
is approximately 3.4μA
LT3837
I
UVLO
IN
referred voltage
(3c) UV Filtering
LT3837
A
C
. The design
UVLO
V
19
IN
R
R
R
3837 F03
A1
A2
B
IN
3837fa
UVLO
is