LT3837EFE-PBF LINER [Linear Technology], LT3837EFE-PBF Datasheet - Page 7

• Manufacturer Part Number: LT3837EFE-PBF
• Description: Isolated No-Opto Synchronous Flyback Controller
• Manufacturer: LINER [Linear Technology]

PIN FUNCTIONS
UVLO (Pin 10): A resistive divider from V
an undervoltage lockout based upon V
When the UVLO pin is below its threshold, the gate drives
are disabled, but the part draws its normal quiescent current
from V
function so V
The bias current on this pin has hysteresis such that the
bias current is sourced when the UVLO threshold is ex-
ceeded. This introduces a hysteresis at the pin equivalent
to the bias current change times the impedance of the
upper divider resistor. The user can control the amount of
hysteresis by adjusting the impedance of the divider. See
the Applications Information for details. Tie the UVLO pin
to V
SENSE
measure primary side switch current through an external
sense resistor. Peak primary side current is used in the
converter control loop. Make Kelvin connections to the
sense resistor to reduce noise problems. SENSE
nects to the ground side. At maximum current (V
maximum voltage) it has a 98mV threshold. The signal is
blanked (ignored) during the minimum turn-on time.
CC
CC
if you are not using this function.
–
(Pin 11), SENSE
. The V
CC
CC
must be great enough to start the part.
undervoltage lockout supersedes this
+
(Pin 12): These pins are used to
IN
IN
level (not V
to this pin sets
C
–
at its
con-
CC
).
C
optional load compensation function. Load compensation
reduces the effects of parasitic resistances in the feedback
sensing path. A 0.1μF ceramic capacitor suffi ces for most
applications. Short this pin to GND in less demanding ap-
plications that don’t require load compensation.
R
resistor. Use of this pin allows for nominal compensation
of parasitic resistances in the feedback sensing path. In
less demanding applications, this resistor is not needed
and this pin can be left open. See Applications Informa-
tion for details.
PGDLY (Pin 15): Pin for external programming resistor to
set delay from synchronous gate turn-off to primary gate
turn-on. See Applications Information for details.
PG (Pin 16): Gate drive pin for the primary side MOSFET
Switch. Large dynamic currents fl ow during voltage transi-
tions. See the Applications Information for details.
GND (Exposed Pad, Pin 17): This is the ground connec-
tion for both signal ground and gate driver grounds. This
GND should be connected to the PCB ground plane for
electrical contact and rated thermal performance. Careful
attention must be paid to ground layout. See Applications
Information for details.
CMP
CMP
(Pin 14): Pin for optional external load compensation
(Pin 13): Pin for external fi lter capacitor for the
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