HCS125D INTERSIL [Intersil Corporation], HCS125D Datasheet

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HCS125D

Manufacturer Part Number
HCS125D
Description
Radiation Hardened Quad Buffer, Three-State
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCS125MS is a Radiation Hardened quad three-state
buffer, each having its own output enable input. A high level on the
enable input puts the output in a high impedance state.
The HCS125MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS125MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCS125DMSR
HCS125KMSR
HCS125D/
Sample
HCS125K/
Sample
HCS125HMSR
(Typ)
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
NUMBER
PART
TEMPERATURE
-55
-55
o
o
RANGE
C to +125
C to +125
+25
+25
+25
10
o
o
o
C
C
C
RAD (Si)/s, 20ns Pulse
5 A at VOL, VOH
o
o
C
C
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
Sample
Die
SCREENING
12
o
LEVEL
C to +125
RAD (Si)/s
o
-9
C
14 Lead SBDIP
14 Lead Ceramic
Flatpack
14 Lead SBDIP
14 Lead Ceramic
Flatpack
Die
2
/mg
Errors/Bit-Day
PACKAGE
123
Pinouts
Functional Diagram
L = Low, H = High, X = Don’t Care, Z = High Impedance
GND
HCS125MS
OE1
OE2
OEn
A1
A2
Y1
Y2
An
MIL-STD-1835 CDFP3-F14, LEAD FINISH C
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
An
H
L
X
FLATPACK PACKAGE (FLATPACK)
14 LEAD CERAMIC DUAL-IN-LINE
14 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
OE1
OE2
INPUTS
A1
Y1
A2
Y2
Quad Buffer, Three-State
1
2
3
4
5
6
7
TRUTH TABLE
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
Radiation Hardened
OEn
H
L
L
Spec Number
14
13
12
11
10
9
8
File Number
14
13
12
11
10
9
8
VCC
OE4
A4
Y4
OE3
A3
Y3
OUTPUT
P
n
Yn
H
L
Z
518831
3559.1
VCC
OE4
A4
Y4
OE3
A3
Y3
Yn

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HCS125D Summary of contents

Page 1

... HCS125DMSR - +125 C Intersil Class S Equivalent o o HCS125KMSR - +125 C Intersil Class S Equivalent o HCS125D/ +25 C Sample Sample o HCS125K/ +25 C Sample Sample o HCS125HMSR +25 C Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 ...

Page 2

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage ...

Page 3

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Propagation Delay TPHL VCC = 4.5V, VIH = 4.5V, Input to Y TPLH VIL = 0V Enable Delay TPZL VCC = 4.5V, VIH = 4.5V, OE toY TPZH VIL = 0V Disable ...

Page 4

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL Output Voltage High VOH VCC = 5.5V, VIH = 3.85V, VIL = 1.65V, IOH = -50 A VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, IOH = -50 A ...

Page 5

CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate group A testing in ...

Page 6

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 7

Propagation Delay Timing Diagram VIH INPUT VS VSS TPLH VOH VS OUTPUT VOL Transition Timing Diagram TTLH VOH 80% 20% OUTPUT VOL VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VIL 0 GND 0 Three-State High Timing Diagrams ...

Page 8

Three-State Low Timing Diagrams VIH INPUT VS VSS TPZL VOZ VT OUTPUT VOL THREE-STATE LOW VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VT 2.25 VW 0.90 GND 0 HCS125MS Three-State Low Load Circuit TPLZ VW UNITS V ...

Page 9

Die Characteristics DIE DIMENSIONS 91(mils) 2.34 x 2.31 (mm) METALLIZATION: Type: AlSi Å Å Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD ...

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