HCS160DMSR INTERSIL [Intersil Corporation], HCS160DMSR Datasheet

no-image

HCS160DMSR

Manufacturer Part Number
HCS160DMSR
Description
Radiation Hardened BCD Decade Synchronous Counter
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset: >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCS160MS is a Radiation Hardened high speed
presettable BCD decade synchronous counter that features an
asynchronous reset and look-ahead carry logic. Counting and
parallel presetting are accomplished synchronously with the low-
to-high transition of the clock. A low level on the synchronous
parallel enable input, SPE, disables counting and allows data at
the preset inputs, P0 - P3, to be loaded into the counter. The
counter is reset by a low on the master reset input, MR. Two count
enables, PE and TE are provided for n-bit cascading. TE also
controls the terminal count output, TC. The terminal count output
indicates a maximum count for one clock pulse and is used to
enable the next cascaded stage to count.
The HCS160MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS160MS is supplied in a 16 lead Ceramic flatpack (K suffix)
or a SBDIP Package (D suffix.)
Ordering Information
HCS160DMSR
HCS160KMSR
HCS160D/Sample
HCS160K/Sample
HCS160HMSR
(Typ)
-Standard Outputs: 10 LSTTL Loads
-Bus Driver Outputs: 15 LSTTL Loads
-VIL = 30% of VCC Max
-VIH = 70% of VCC Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A @ VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
-55
-55
RAD (Si)/s
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
-9
C
2
/mg
Errors/Bit-Day
o
o
C
C
183
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
BCD Decade Synchronous Counter
SCREENING LEVEL
Pinouts
GND
HCS160MS
MR
CP
PE
P0
P1
P2
P3
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
16 LEAD CERAMIC DUAL-IN-LINE
16 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
MR
CP
PE
P0
P1
P2
P3
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TOP VIEW
TOP VIEW
Radiation Hardened
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
Spec Number
16
15
14
13
12
11
10
9
File Number
PACKAGE
16
15
14
13
12
11
10
9
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE
518834
2296.2
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE

Related parts for HCS160DMSR

HCS160DMSR Summary of contents

Page 1

... CMOS/SOS Logic Family. The HCS160MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix.) Ordering Information PART NUMBER TEMPERATURE RANGE HCS160DMSR HCS160KMSR HCS160D/Sample HCS160K/Sample HCS160HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. ...

Page 2

Functional Block Diagram P0 3 SPE GND VCC OPERATING MODE MR Reset (Clear) L Parallel Load H H Count H Inhibit ...

Page 3

Absolute Maximum Ratings Supply Voltage (VCC -0.5V to +7.0V Input Voltage Range, All Inputs . . ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL TPHL, VCC = 4.5V TPLH TPHL, VCC = 4.5V TPLH TPHL, VCC = 4.5V TPLH TPHL VCC ...

Page 5

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL Output Current IOH VCC = 4.5V, VIN = VCC or GND, (Source) VOUT = VCC -0.4V Output Voltage Low VOL VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL ...

Page 6

CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate Group A testing in ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VIL 0 GND 0 HCS160MS AC Load Circuit TPHL TTHL 80% ...

Page 9

Die Characteristics DIE DIMENSIONS: 104 x 86 mils METALLIZATION: Type: AlSi Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 ...

Related keywords