HCS161DMSR INTERSIL [Intersil Corporation], HCS161DMSR Datasheet

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HCS161DMSR

Manufacturer Part Number
HCS161DMSR
Description
Radiation Hardened Synchronous Counter
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Cosmic Ray Upset Immunity 2 x 10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCS161MS is a Radiation Hardened 4-Input Binary;
synchronous counter featuring asynchronous reset and look-
ahead carry logic. The HCS161 has an active-low master reset to
zero, MR. A low level at the synchronous parallel enable, SPE,
disables counting and allows data at the preset inputs (p0 - p3) to
load the counter. The data is latched to the outputs on the posi-
tive edge of the clock input, CP. The HCS161MS has two count
output, IC. The terminal count output indicates a maximum count
for one clock pulse and is used to enable the next cascaded
stage to count.
The HCS161MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS161MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCS161DMSR
HCS161KMSR
HCS161D/Sample
HCS161K/Sample
HCS161HMSR
Day (Typ)
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
-55
-55
RAD (Si)/s
-9
Error/Bit Day (Typ)
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/Bit-
193
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
SCREENING LEVEL
Pinouts
GND
MR
CP
HCS161MS
PE
P0
P1
P2
P3
FLATPACK PACKAGE (FLATPACK)
16 LEAD CERAMIC DUAL-IN-LINE
16 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
MIL-STD-1835 CDFP4-F16
MR
MIL-STD-1835 CDIP2-T16
CP
PE
P0
P1
P2
P3
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Synchronous Counter
TOP VIEW
TOP VIEW
Radiation Hardened
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
Spec Number
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
File Number
9
PACKAGE
TC
Q0
Q1
Q2
Q3
TE
SPEN
VCC
518755
2469.2
TC
Q0
Q1
Q2
Q3
TE
SPE
VCC

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HCS161DMSR Summary of contents

Page 1

... CMOS/SOS Logic Family. The HCS161MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCS161DMSR HCS161KMSR HCS161D/Sample HCS161K/Sample HCS161HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. ...

Page 2

Functional Diagram GND 8 SPE 9 T FF0 SPE OPERATING MODE MR Reset (Clear) L Parallel Load H H Count H Inhibit H ...

Page 3

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL TPHL VCC = 4.5V TPLH TPHL VCC = 4.5V TPLH TPHL VCC = 4.5V TPLH TPHL VCC = 4.5V MR ...

Page 5

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL Output Voltage Low VOL VCC = 4.5V and 5.5V, VIH = 0.70(VCC), VIL = 0.30(VCC), IOL = 50 A Output Voltage High VOH VCC = 4.5V and 5.5V, VIH ...

Page 6

CONFORMANCE GROUPS METHOD Group E Subgroup 2 5005 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OPEN GROUND STATIC BURN-IN I TEST CONDITIONS (Note ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VIL 0 GND 0 All Intersil semiconductor products are manufactured, assembled ...

Page 9

Die Characteristics DIE DIMENSIONS: 104 x 86 mils 2650 x 2190mm METALLIZATION: Type: AlSi Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND ...

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