HCS163D INTERSIL [Intersil Corporation], HCS163D Datasheet

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HCS163D

Manufacturer Part Number
HCS163D
Description
Radiation Hardened Synchronous Presettable Counter
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
1.HCS163D.pdf (9 pages)
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset: >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCS163MS is a Radiation Hardened synchronous
presettable binary counter that features lookahead carry logic for
use in high speed counting applications. Counting and parallel
load, and presetting are all accomplished synchronously with the
positive transition of the clock.
The HCS163MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS163MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCS163DMSR
HCS163KMSR
HCS163D/Sample
HCS163K/Sample
HCS163HMSR
(Typ)
- VIL = 30% of VCC
- VIH = 70% of VCC
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
-55
-55
RAD (Si)/s
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
-9
C
2
/mg
Errors/Bit-Day
o
o
C
C
220
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
SCREENING LEVEL
Pinouts
Synchronous Presettable Counter
GND
HCS163MS
MR
CP
PE
P0
P1
P2
P3
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
16 LEAD CERAMIC DUAL-IN-LINE
16 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
MR
CP
PE
P0
P1
P2
P3
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TOP VIEW
TOP VIEW
Radiation Hardened
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
Spec Number
16
15
14
13
12
11
10
9
File Number
PACKAGE
16
15
14
13
12
11
10
9
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE
518835
3087.1
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE

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HCS163D Summary of contents

Page 1

... The HCS163MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCS163DMSR HCS163KMSR HCS163D/Sample HCS163K/Sample HCS163HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HCS163MS Synchronous Presettable Counter ...

Page 2

Functional Block Diagram SPE 1 MR VCC 2 CP OPERATING MODE MR Reset (clear) l Parallel Load h (Note 3) h (Note 3) Count h (Note 3) Inhibit h (Note 3) h (Note 3) ...

Page 3

Absolute Maximum Ratings Supply Voltage (VCC -0.5V to +7.0V Input Voltage Range, All Inputs . . ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Propagation Delay TPHL, VCC = 4. TPLH Propagation Delay TPHL, VCC = 4. TPLH Propagation Delay TPHL, VCC = 4. TPLH NOTES: 1. ...

Page 5

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Supply Current ICC Output Current (Sink) IOL Output Current IOH (Source) Output Voltage Low VOL Output Voltage High VOH Input Leakage Current IIN Noise Immunity FN Functional Test Propagation Delay ...

Page 6

CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate group A testing in ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

Propagation Delay Timing Diagram and Load Circuit VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VIL 0 GND 0 DUT 50pF RL = 500 ...

Page 9

Die Characteristics DIE DIMENSIONS: 104 x 86 mils METALLIZATION: Type: AlSi Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY < 2 A/cm BOND PAD SIZE: ...

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