X5083SI INTERSIL [Intersil Corporation], X5083SI Datasheet

no-image

X5083SI

Manufacturer Part Number
X5083SI
Description
CPU Supervisor with 9Kbit SPI EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
CPU Supervisor with 8Kbit SPI EEPROM
This device combines four popular functions, Power-on Reset
Control, Watchdog Timer, Supply Voltage Supervision, and
Block Lock Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET active for a period of time. This
allows the power supply and oscillator to stabilize before the
processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller fails to
restart a timer within a selectable time out interval, the device
activates the RESET signal. The user selects the interval
from three preset values. Once selected, the interval does
not change, even after cycling the power.
The device’s low V
system from low voltage conditions, resetting the system
when V
asserted until V
stabilizes. Five industry standard V
available, however, Intersil’s unique circuits allow the threshold
to be reprogrammed to meet custom requirements or to fine-
tune the threshold for applications requiring higher precision.
Pinouts
CC
falls below the minimum V
CS/WDI
CS/WDI
CC
RESET
V
V
WP
SO
CC
returns to the proper operating level and
SO
CC
SS
8 Ld SOIC, 8 Ld PDIP
detection circuitry protects the user’s
8 Ld TSSOP
1
2
3
4
1
2
3
4
®
X5083
X5083
1
TRIP
8
7
6
5
8
7
6
5
Data Sheet
CC
thresholds are
SCK
SI
V
WP
V
RESET
SCK
SI
trip point. RESET is
SS
CC
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Low V
• Selectable time out watchdog timer
• Long battery life with low power consumption
• 8Kbits of EEPROM
• Save critical data with Block Lock
• Built-in inadvertent write protection
• SPI Interface - 3.3MHz clock rate
• Minimize programming time
• SPI modes (0,0 & 1,1)
• Available packages
• Pb-free plus anneal available (RoHS compliant)
Applications
• Communications Equipment
• Industrial Systems
• Computer Systems
• Battery Powered Equipment
September 16, 2005
- Four standard reset threshold voltages
- Re-program low V
- Reset signal valid to V
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
- Block lock first or last page, any 1/4 or lower 1/2 of
- Write enable latch
- Write protect pin
- 16 byte page write mode
- 5ms write cycle time (typical)
- 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
- Routers, Hubs, Switches
- Set Top Boxes
- Process Control
- Intelligent Instrumentation
- Desktop Computers
- Network Servers
4.63V, 4.38V, 2.93V, 2.63V
special programming sequence
EEPROM array
All other trademarks mentioned are the property of their respective owners.
CC
|
detection and reset assertion
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
CC
reset threshold voltage using
CC
= 1V
memory
X5083
FN8127.2

Related parts for X5083SI

X5083SI Summary of contents

Page 1

Data Sheet CPU Supervisor with 8Kbit SPI EEPROM This device combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space ...

Page 2

Typical Application 2.7-5.0V VCC 10K X5083 RESET CS SCK VSS Block Diagram TRIP WATCHDOG TRANSITION DETECTOR CS/WDI COMMAND SI DECODE & SO CONTROL LOGIC SCK WP PROTECT LOGIC 2 X5083 VCC uC ...

Page 3

... X5083P AM X5083S8-4.5A X5083 AL X5083S8Z-4.5A (Note) X5083 Z AL X5083S8I-4.5A* X5083 AM X5083S8IZ-4.5A* (Note) X5083 Z AM X5083V8-4.5A 583AL X5083V8I-4.5A 583AM X5083P X5083P X5083PI X5083P I X5083SI X5083 I X5083S8 X5083 X5083S8Z (Note) X5083 Z X5083S8I* X5083 I X5083S8IZ* (Note) X5083 Z I X5083V8 X583 X5083V8I 583I X5083P-2.7A X5083P AN X5083PI-2.7A X5083P AP X5083S8-2 ...

Page 4

Pin Description PIN (SOIC/ PIN PDIP) TSSOP NAME 1 3 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin high impedance state. Unless a nonvolatile write cycle is underway, the device will ...

Page 5

To set the new V voltage, apply the desired V TRIP threshold voltage to the V pin and tie the WP pin to the CC programming voltage V . Then send a WREN command, P followed by a write of ...

Page 6

V P Adjust V TRIP Adj. Run New V Applied = CC Old V Applied + Error CC Emax = Maximum Desired Error 6 X5083 X5083 FIGURE 3. SAMPLE V RESET CIRCUIT ...

Page 7

SPI Serial Memory The memory portion of the device is a CMOS serial EEPROM array with Intersil’s block lock protection. The array is internally organized The device features a Serial Peripheral Interface (SPI) and software protocol allowing ...

Page 8

Watchdog Timer The watchdog timer bits, WD0 and WD1, select the watchdog time out period. These nonvolatile bits are programmed with the WRSR instruction. A change to the Watchdog Timer, either setting a new time out period or turning it ...

Page 9

Data Protection The following circuitry has been included to prevent inadvertent writes: • A WREN instruction must be issued to set the write enable latch. • CS must come HIGH at the proper clock count in order to start a ...

Page 10

CS SCK SI High Impedance SCK Instruction SCK Data Byte FIGURE 8. ...

Page 11

SCK READ STATUS INSTRUCTION SI NONVOLATILE WRITE IN PROGRESS SO SO MSB HIGH while in the Nonvolatile write cycle SCK READ STATUS ...

Page 12

CS SCK SI Non-volatile Write Operation FIGURE 11. END OF NONVOLATILE WRITE (NO POLLING) Symbol Table WAVEFORM INPUTS OUTPUTS Must be Will be steady steady May change Will change from LOW from LOW to HIGH to HIGH May change Will ...

Page 13

Absolute Maximum Ratings Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . .-65°C to 135°C Storage Temperature . . . . . . . . ...

Page 14

Equivalent A.C. Load Circuit 1.64kΩ SO OUTPUT 1.64kΩ 100pF AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified) SYMBOL DATA INPUT TIMING f Clock frequency SCK t Cycle time CYC t CS lead time LEAD ...

Page 15

Serial Output Timing CS SCK MSB Out ADDR SI LSB IN Serial Input Timing CS t LEAD SCK MSB IN High Impedance SO Power-Up and Power-Down Timing V TRIP PURST 0 ...

Page 16

RESET Output Timing SYMBOL V Reset trip point voltage, X5083PT-4.5A (Note 6) TRIP Reset trip point voltage, X5083PT Reset trip point voltage, X5083PT-2.7A Reset trip point voltage, X5083PT-2.7 t Power-up reset time out PURST t (Note 5) V detect to ...

Page 17

V Programming Timing Diagram TRIP TRIP VPS CS SCK SI 06h WREN V Programming Parameters TRIP PARAMETER t V program enable voltage setup time VPS TRIP t V program enable voltage ...

Page 18

Packaging Information Half Shoulder Width On All End Pins Optional .073 (1.84) Typ. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 18 X5083 8-Lead Plastic Dual In-Line Package Type P ...

Page 19

Packaging Information 8-Lead Plastic Small Outline Gull Wing Package Type S Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 19 X5083 Pin 1 0.014 (0.35) ...

Page 20

Packaging Information 0° - 8° See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil ...

Related keywords