X5168 INTERSIL [Intersil Corporation], X5168 Datasheet - Page 6

• Manufacturer Part Number: X5168
• Description: CPU Supervisor with 16Kbit SPI EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

SPI Serial Memory
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
Note:
INSTRUCTION NAME
WREN CMD
WRDI/RFLB
WEL
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
0
1
1
1
WRITE
WREN
WRSR
RSDR
READ
SFLB
STATUS REGISTER
WPEN
INSTRUCTION FORMAT*
X
1
0
X
6
0000 0000
0000 0100
0000 0101
0000 0001
0000 0010
0000 0110
0000 0011
DEVICE PIN
WP#
X
X
0
1
TABLE 2. BLOCK PROTECT MATRIX
TABLE 1. INSTRUCTION SET
™
Set the write enable latch (enable write operations)
Set flag bit
Reset the write enable latch/reset flag bit
Read status register
Write status register (watchdog, block lock, WPEN & flag bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
cell,
X5168, X5169
PROTECTED BLOCK
Protected
Protected
Protected
Protected
BLOCK
Write Enable Latch
The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid write cycle.
Status Register
The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows:
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
WPEN
7
FLB
UNPROTECTED BLOCK
6
OPERATION
Protected
Writable
Writable
Writable
BLOCK
5
0
4
0
BL1
3
WPEN, BL0, BL1 WD0,
STATUS REGISTER
BL0
2
Protected
Protected
Writable
Writable
WD1
September 16, 2005
WEL
1
FN8130.1
WIP
0