M40Z300MH1TR STMICROELECTRONICS [STMicroelectronics], M40Z300MH1TR Datasheet - Page 8

• Manufacturer Part Number: M40Z300MH1TR
• Description: 5V or 3V NVRAM Supervisor for Up to 8 LPSRAMs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M40Z300, M40Z300W
Figure 8. Address-Decode Time
Note: During system design, compliance with the SRAM timing parameters must comprehend the propagation delay between E1
Data Retention Lifetime Calculation
Most low power SRAMs on the market today can
be used with the M40Z300/W NVRAM SUPERVI-
SOR. There are, however some criteria which
should be used in making the final choice of which
SRAM to use. The SRAM must be designed in a
way where the chip enable input disables all other
inputs to the SRAM. This allows inputs to the
M40Z300/W and SRAMs to be “Don't Care” once
V
guarantee data retention down to V
chip enable access time must be sufficient to meet
the system needs with the chip enable propaga-
tion delays included. If the SRAM includes a sec-
ond chip enable pin (E2), this pin should be tied to
V
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use.
The data retention current value of the SRAMs can
then be added to the I
W to determine the total current requirements for
data retention. The available battery capacity for
the SNAPHAT
by this current to determine the amount of data re-
tention available (see
CAUTION: Take care to avoid inadvertent dis-
charge through V
battery has been attached.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
8/21
CC
OUT
falls below V
E4
.
CON
.
A, B
E
E1 CON - E4 CON
®
of your choice can then be divided
PFD
OUT
(min). The SRAM should also
Table 13., page
BAT
and E1
value of the M40Z300/
CON
CC
- E4
= 2.0V. The
19).
CON
tAS
after
tEDL
Power-on Reset Output
All microprocessors have a reset input which forc-
es them to a known state when starting. The
M40Z300/W has a reset output (RST) pin which is
guaranteed to be low within t
This signal is an open drain configuration. An ap-
propriate pull-up resistor should be chosen to con-
trol the rise time. This signal will be valid for all
voltage conditions, even when V
Once V
age V
t
Battery Low Pin
The M40Z300/W automatically performs battery
voltage monitoring upon power-up, and at factory-
programmed time intervals of at least 24 hours.
The Battery Low (BL) pin will be asserted if the
battery voltage is found to be less than approxi-
mately 2.5V. The BL pin will remain asserted until
completion of battery replacement and subse-
quent battery low monitoring tests, either during
the next power-up sequence or the next scheduled
24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below
2.5V and may not be able to maintain data integrity
in the SRAM. Data should be considered suspect,
and verified as correct. A fresh battery should be
installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal V
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT
should be replaced with valid V
device.
REC
to allow the power supply to stabilize.
PFD
CC
, an internal timer keeps RST low for
exceeds the power failure detect volt-
tEDH
AI02551
WPT
CC
CC
of V
equals V
applied to the
PFD
(see 7).
CC
®
SS
CON
top
.
is
-