AK5702VN AKM [Asahi Kasei Microsystems], AK5702VN Datasheet

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AK5702VN

Manufacturer Part Number
AK5702VN
Description
4-Channel ADC with PLL & MIC-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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AK5702VN-L
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The AK5702 features a 4-channel ADC. Input circuits include a Microphone-Amplifier with programmable
gain and an ALC (Auto Level Control) circuit, making it ideal for consumer microphone array applications.
On-chip PLL and TDM audio format makes it easy to connect with DSP. The AK5702 has a software
compatibility with stereo version, AK5701.
MS0623-E-00
1. Recording Function
2. Sampling Rate:
3. PLL Input Clock:
4. Master/Slave mode
5. Audio Interface Format: MSB First, 2’s complement
6. μP I/F: 3-wire Serial or I2C Bus (Ver 1.0, 400kHz Mode)
7. Power Supply:
8. Power Supply Current: 13 mA ( EXT Slave Mode)
9. Ta = −30 ∼ 85°C
10. Package: 32pin QFN (5mm x 5mm)
11. Register Compatible with AK5701
- 4-Channel ADC
- 3:1 Stereo Input Selector
- Full-differential or Single-ended Input
- MIC Amplifier (+36dB/+30dB/+15dB/0dB)
- Input Voltage: 1.8Vpp@AVDD=3.0V (= 0.6 x AVDD)
- ADC Performance:
- Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
- Digital ALC
- Input Digital Volume (+36dB ∼ −54dB, 0.375dB Step, Mute)
- PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (BCLK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (MCKI pin):
- PLL Master Mode:
- EXT Slave Mode:
- MCKI pin:
- LRCK pin: 1fs
- BCLK pin: 32fs/64fs
- DSP Mode, 16bit MSB justified, I
- Cascade TDM interface
- AVDD: 2.4 ∼ 3.6V
- DVDD: 1.6 ∼ 3.6V (Stereo Mode)
- DVDD: 2.0 ∼ 3.6V (TDM128 Mode, 16bit x 8ch)
- DVDD: 2.7 ∼ 3.6V (TDM256 Mode, 32bit x 8ch)
27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz,
11.2896MHz
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs),
7.35kHz ∼ 13kHz (1024fs)
S/(N+D): 83dB, DR, S/N: 89dB@MGAIN=0dB
S/(N+D): 83dB, DR, S/N: 87dB@MGAIN=+15dB
GENERAL DESCRIPTION
4-Channel ADC with PLL & MIC-AMP
FEATURES
- 1 -
2
S
AK5702
[AK5702]
2007/06

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AK5702VN Summary of contents

Page 1

The AK5702 features a 4-channel ADC. Input circuits include a Microphone-Amplifier with programmable gain and an ALC (Auto Level Control) circuit, making it ideal for consumer microphone array applications. On-chip PLL and TDM audio format makes it easy to connect ...

Page 2

Block Diagram LIN1 RIN1 S LIN2 E RIN2 L S LIN5 E RIN5 L S LIN3 E RIN3 L LIN4 RIN4 MPWRA MPWRB VCOM AVDD VSS1 VCOC PLL MCKO MCKI MS0623-E-00 ALC or ADCA HPF MIX IVOL ALC ADCB ...

Page 3

... Comparison with AK5701 Function # of ADC channel Input Selector Cascade TDM interface Bypass mode uP I/F Package MS0623-E-00 −30 ∼ +85°C 32pin QFN (0.5mm pitch) Evaluation board for AK5702 AK5702VN Top View AK5701 2 2 stereo No Yes 3-wire 24pin QFN (4mm x 4mm [AK5702] CSN 16 ...

Page 4

No. Pin Name I/O 1 MPWRB O 2 VCOM O 3 PDN I 4 CAD0 I 5 DVDD - 6 VSS2 - 7 LRCK I/O 8 BCLK I/O 9 SDTOB O 10 SDTOA O 11 MCKO O 12 TEST I ...

Page 5

Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name MPWRA, MPWRB, VCOC, LIN1/LINA+, RIN1/LINA−, LIN2/RINA−, RIN2/RINA+, Analog LIN3/LINB+, RIN3/LINB−, LIN4/RINB−, RIN4/RINB+, RIN5, LIN5 SDTOA, SDTOB, MCKO Digital MCKI, TDMIN (VSS1, VSS2=0V; ...

Page 6

AVDD, DVDD=3.0V; VSS1, VSS2=0V; EXT Slave Mode; MCKI=11.2896MHz, fs=44.1kHz, BCLK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) Parameter MIC Amplifier: LIN1-5, RIN1-5 pins; MDIFA1-2 = MDIFB1-2 bits = “00” (Single-ended inputs) LIN1-4, RIN1-4 pins MGAIN1-0 ...

Page 7

Note 9. Input voltage is proportional to AVDD voltage. Vin = 0.107 x AVDD (typ)@MGAIN1-0 bits = “01” (+15dB), Vin = 0.6 x AVDD (typ)@MGAIN1-0 bits = “00” (0dB). Note 10. 83dB(typ)@MGAIN=0dB, 72dB(typ)@MGAIN=+30dB, 66dB (typ) @MGAIN=+36dB Note 11. 89dB(typ)@MGAIN=0dB, 77dB(typ)@MGAIN=+30dB, ...

Page 8

AVDD=2.4 ∼ 3.6V; DVDD=1.6 - 3.6V (Note 17); C Parameter PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency Pulse Width Low Pulse Width High MCKO Output Timing Frequency Duty Cycle Except 256fs at fs=32kHz, ...

Page 9

Parameter PLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Frequency DSP Mode: Pulse Width High Except DSP Mode: Duty Cycle BCLK Input Timing Period Pulse Width Low Pulse Width High PLL Slave Mode (PLL Reference Clock ...

Page 10

Parameter External Master Mode MCKI Input Timing Frequency 256fs 512fs 1024fs Pulse Width Low Pulse Width High LRCK Output Timing Frequency Stereo DSP Mode: Pulse Width High Stereo I2S, MSB Justified Mode: Duty Cycle TDM128 Mode: Pulse Width High TDM256 ...

Page 11

Parameter Audio Interface Timing (Stereo DSP Mode) Master Mode LRCK “↑” to BCLK “↑” (Note 18) LRCK “↑” to BCLK “↓” (Note 19) BCLK “↑” to SDTO (BCKP bit = “0”) BCLK “↓” to SDTO (BCKP bit = “1”) Slave ...

Page 12

Parameter Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN Edge to CCLK “↑” (Note 22) CCLK “↑” to CSN Edge (Note 22) 2 Control Interface Timing ...

Page 13

Timing Diagram MCKI LRCK BCLK MCKO LRCK BCLK SDTO Figure 3. Audio Interface Timing (PLL/EXT Master mode & Normal mode) MS0623-E-00 1/fCLK tCLKH tCLKL 1/fs tLRCKH tLRCKL Duty = tLRCKH 100 tBCK tBCKH tBCKL dBCK = ...

Page 14

LRCK BCLK (BCKP = "0") BCLK (BCKP = "1") SDTO Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”) LRCK BCLK (BCKP = "1") BCLK (BCKP = "0") SDTO Figure 5. Audio Interface Timing (PLL/EXT ...

Page 15

LRCK BCLK SDTO TDMIN Figure 6. Audio Interface Timing (PLL/EXT Master mode & TDM mode) MS0623-E-00 tMBLR tBSD tTDMS tTDMH - 15 - 50%DVDD dBCK 50%DVDD 50%DVDD VIH VIL [AK5702] 2007/06 ...

Page 16

LRCK BCLK (BCKP = "0") BCLK (BCKP = "1") Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BCLK pin & DSP mode; MSBS = 0) LRCK BCLK (BCKP = "1") BCLK (BCKP = "0") Figure ...

Page 17

MCKI LRCK BCLK MCKO Figure 9. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode) LRCK BCLK (BCKP = "0") BCLK (BCKP = "1") SDTO Figure 10. Audio Interface Timing (PLL Slave mode & ...

Page 18

LRCK BCLK (BCKP = "1") BCLK (BCKP = "0") SDTO Figure 11. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 1) MCKI LRCK BCLK MS0623-E-00 tLRCKH tLRB tBSD 1/fCLK tCLKH tCLKL 1/fs Duty = tLRCKH x fs ...

Page 19

LRCK tBLR BCLK SDTO Figure 13. Audio Interface Timing (PLL/EXT Slave mode) LRCK tBLR BCLK SDTO TDMIN Figure 14. Audio Interface Timing (PLL/EXT Slave mode & TDM mode) MS0623-E-00 tLRB tLRD tBSD MSB tLRB tBSD tTDMS tTDMH - 19 - ...

Page 20

CSN tCSH CCLK CDTI CSN CCLK CDTI D2 SDA tBUF tLOW SCL tHD:STA Stop Start MS0623-E-00 tCSS tCCKL tCDS C1 Figure 15. WRITE Command Input Timing D1 Figure 16. WRITE Data Input Timing tHIGH tR tF tHD:DAT tSU:DAT tSU:STA Start ...

Page 21

PMADAL bit or PMADAR bit or PMADBL bit or PMADBR bit SDTO PDN MS0623-E-00 tPDV Figure 18. Power Down & Reset Timing 1 tPD Figure 19. Power Down & Reset Timing [AK5702] 50%DVDD VIL 2007/06 ...

Page 22

System Clock There are the following five clock modes to interface with external devices (Table 1 and Table 2.) Mode PLL Master Mode (Note 27) PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 (PLL ...

Page 23

PLL Mode When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK5702 ...

Page 24

When PLL reference clock input is LRCK or BCLK pin, the sampling frequency is selected by FS3 and FS2 bits (Table 6). FS3 bit FS2 bit Mode Don’t care Others Table 6. Setting of ...

Page 25

PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz) is input to MCKI pin, the MCKO, BCLK and LRCK clocks are generated by ...

Page 26

PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to MCKI, BCLK or LRCK pin. The required clock to the AK5702 is generated by an internal ...

Page 27

EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK5702 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible ...

Page 28

EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”, TE3-0 bits = “0101”, TMASTER bit = “1”) The AK5702 becomes EXT Master Mode by setting as Figure 63. Master clock is input from MCKI pin, the internal ...

Page 29

Audio Interface Format Fore types of data format are available and are selected by setting the M/S, TDM1-0, DIF1-0 bits (Table 14, Table 15, Table 16). In all modes, the serial data is MSB first, 2’s complement format. Audio ...

Page 30

In DSP mode 0, the audio I/F timing is changed by BCKP and MSBS bits. When BCKP bit is “0”, SDTO data is output by rising edge (“↑”) of BCLK/BCLK. When BCKP bit is “1”, SDTO data is output by ...

Page 31

LRCK (M/S=0) LRCK (M/S= BCLK(32fs) Lch 8 SDTOA/B( 15:MSB, 0:LSB Figure 25. Mode 0, 4 Timing (Stereo Mode, DSP Mode 0, MSBS = “0”, BCKP = “0”) LRCK (M/S=0) LRCK (M/S= ...

Page 32

LRCK BCLK(32fs SDTO( BCLK(64fs SDTOA/B(o) 15:MSB, 0:LSB Figure 29. Mode 2, 6 Timing (Stereo Mode, MSB justified) LRCK ...

Page 33

LRCK (Mode 15) LRCK (Mode 11) BCLK (128fs) SDTOB ( BCLK Figure 32. Mode 11, 15 Timing (TDM128 mode, I LRCK (Mode 22) LRCK (Mode 18) BCLK (256fs) SDTOB ( BCLK Figure 33. ...

Page 34

Cascade TDM Mode The AK5702 supports cascading two devices in a daisy chain configuration at TDM mode. In this mode, SDTOB pin of device #1 is connected to TDMIN pin of device #2. SDTOB pin of ...

Page 35

AK5702 #1 AK5702 #2 Figure 37. Cascade TDM Connection example (TDM256, MSB justified) LRCK BCLK(256fs) #1 SDTOB( BCLK #2 TDMIN( BCLK #2 SDTOB( L1-#2 32 BCLK MS0623-E-00 MCLK LRCK BLCK ...

Page 36

Mono/Stereo Selection PMADAL, PMADAR and MIXA bits select mono or stereo mode of ADCA output data. PMADBL, PMADBR and MIXB bits select mono or stereo mode of ADCB output data. ALC operation (ALC bit = “1”) or digital volume ...

Page 37

MIC/LINE Input Selector The AK5702 has input selector. When MDIF1 and MDIF2 bits are “0”, INAL and INAR bits select LIN1/LIN2 and RIN1/RIN2, INBL and INBR bits select LIN3/LIN4 and RIN3/RIN4 respectively. INA5L and INA5R bits also select LIN5 ...

Page 38

AK5702 LIN1/LINA+ pin RIN1/LINA− pin RIN2/RINA+ pin LIN2/RINA− pin LIN5 pin RIN5 pin LIN3/LINB+ pin RIN3/LINB− pin RIN4/RINB+ pin LIN4/RINB− pin MS0623-E-00 INA5L bit INAL bit MDIFA1 bit INA5R bit INAR bit MDIFA2 bit INB5L bit INBL bit MDIFB1 bit ...

Page 39

Figure 40. Connection Example for Full-differential Mic Input (MDIFA1/2 bits = “1”) MGAINA1-0 bits MGAINB1-0 bits Don’t care Don’t care 00 00 01,10,11 01,10,11 00 01,10,11 Don’t care Don’t care 01,10,11 01,10,11 01,10,11 ■ MIC Gain Amplifier ...

Page 40

MIC Power Figure 41. ADCA MIC Block Circuit MDIFA (MDIFA1=MDIFA2=“0”) MIC Power Figure 42. ADCB MIC Block Circuit MDIFB (MDIFB1=MDIFB2=“0”) MS0623-E-00 MPWRA pin LIN1 pin RIN1 pin LIN2 pin RIN2 pin LIN5 pin RIN5 pin MPWRB pin LIN3 pin RIN3 ...

Page 41

ALC Operation When ALCA bit = “1”, ALC operation is done for 2ch of ADCA. When ALCB bit = “1”, ALC operation is done for 2ch of ADCB. Volumes of Lch and Rch always change in common during ALC ...

Page 42

ZELMNA/B LMATA/ ZTMA/B1 ZTMA/ ALC Recovery Operation The ALC recovery operation waits for the WTMA/B2-0 bits (Table 31 set after completing the ALC limiter operation. If the ...

Page 43

RGA/ REFA/B7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H Table 33. Reference Level at ALC Recovery operation RFSTA/B1 bit MS0623-E-00 RGA/B0 GAIN STEP 0 1 step 0.375dB ...

Page 44

Example of ALC Operation Table 35 shows the examples of the ALC setting for mic recording. Register Name Comment LMTHA/B1-0 Limiter detection Level ZELMNA/B Limiter zero crossing detection ZTMA/B1-0 Zero crossing timeout period Recovery waiting period WTMA/B2-0 *WTMA/B 2-0 ...

Page 45

Input Digital Volume (Manual Mode) The input digital volume becomes a manual mode when ALC4 bit is “0” and ALCA/B bit is “0”. This mode is used in the case shown below. 1. After exiting reset state, set-up the ...

Page 46

When writing to the IVA/BL7-0 and IVA/BR7-0 bits continuouslly, the control register should be written by an interval more than zero crossing timeout. If not, IVA/BL and IVA/BR are not changed since zero crossing counter is reset at every write ...

Page 47

ALC 4ch Link Mode sequence Figure 47 shows the 4ch Link ALC Mode sequence at ALCA bit = ALCB bit = “0” ALC4 bit PMADAL or (1) PMADAR bit (2) PMADBL or PMADBR bit ALCA bit ALCB bit ADCA ...

Page 48

System Reset Upon power-up, the AK5702 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADAL or ...

Page 49

Serial Control Interface (1) 3-wire Serial Control Mode (I2C pin = “L”) Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2-bit Chip address ...

Page 50

I C-bus Control Mode (I2C pin = “H”) The AK5702 supports the fast-mode I (2)-1. WRITE Operations Figure 47 shows the data transfer sequence for the I HIGH to LOW transition on the SDA line while SCL is ...

Page 51

READ Operations Set the R/W bit = “1” for the READ operation of the AK5702. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the ...

Page 52

SDA SCL start condition DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START CONDITION SDA SCL MS0623-E-00 S Figure 53. START and STOP Conditions 2 1 Figure 54. Acknowledge on the I data line change stable; ...

Page 53

Register Map Addr Register Name 00H Power Management 01H PLL Control 02H Signal Select 03H Mic Gain Control 04H Audio Format Select 05H fs Select 06H Clock Output Select 07H Volume Control 08H Lch Input Volume Control 09H Rch ...

Page 54

Register Definitions Addr Register Name 00H Power Management Default PMADAL: MIC-AmpA Lch and ADCA Lch Power Management 0: Power down (default) 1: Power up PMADAR: MIC-AmpA Rch and ADCA Rch Power Management 0: Power down (default) 1: Power up ...

Page 55

Addr Register Name 02H Signal Select Default INAL: ADCA Lch Input Source Select 0: LIN1 pin (default) 1: LIN2 pin INAR: ADCA Rch Input Source Select 0: RIN1 pin (default) 1: RIN2 pin MDIFA1: ADCA Lch Input Type Select 0: ...

Page 56

Addr Register Name 04H Audio Format Select Default DIF1-0: Audio Interface Format (Table 14) 2 Default: “11” BCKP: BCLK/BCLK Polarity at DSP Mode (Table 17) 0: SDTO is output by the rising edge (“↑”) of BCLK/BCLK. (default) 1: ...

Page 57

Addr Register Name 07H Volume Control Default IVOLAC: Input Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When IVOLAC bit = “1”, IVAL7-0 bits control both Lch and Rch volume level, while register values of IVAL7-0 bits are ...

Page 58

Addr Register Name 0CH ALC Mode Control 2 Default LMTHA1-0: ALCA Limiter Detection Level / Recovery Counter Reset Level (Table 28) Default: “00” RGA1-0: ALCA Recovery GAIN Step (Table 32) Default: “00” LMATA1-0: ALCA Limiter ATT Step (Table 29) Default: ...

Page 59

Addr Register Name 10H Power Management Default PMADBL: MIC-AmpB Lch and ADCB Lch Power Management 0: Power down (default) 1: Power up PMADBR: MIC-AmpB Rch and ADCB Rch Power Management 0: Power down (default) 1: Power up When the PMADBL ...

Page 60

Addr Register Name 14H Audio Format Select Default MIXB: ADCB Output Data Select (Table 19) 0: Normal operation (default) 1: (L+R)/2 Addr Register Name 15H fs Select Default HPFB1-0: Offset Cancel HPF Cut-off Frequency and ADCB Initialization Cycle (Table 21, ...

Page 61

Addr Register Name 1AH Timer Select Default WTM2-0: ALCB Recovery Waiting Period (Table 31) Default: “00” (128/fs) A period of recovery operation when any limiter operation does not occur during the ALCB operation. ZTM1-0: ALCB Limiter/Recovery Operation Zero Crossing Timeout ...

Page 62

... Mic input AC coupling capacitor should be 1μF or less to start the recording within 100ms. Figure 56. Typical Connection Diagram (MIC Input) MS0623-E-00 SYSTEM DESIGN MIC 0 (Note) Power Supply 2.4 ∼ 3. LIN1 26 RIN1 LIN5 27 AK5702VN 28 RIN5 29 LIN4 Top View RIN4 30 LIN3 31 RIN3 Power Supply 1.6 ∼ 3. [AK5702] ...

Page 63

... When the AK5702 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4. 0 parallel with Cp+Rp improves PLL jitter characteristics. Figure 57. Typical Connection Diagram (Line Input) MS0623-E-00 LINE 0 (Note) Power Supply 2.4 ∼ 3. LIN1 26 RIN1 LIN5 27 AK5702VN 28 RIN5 LIN4 29 Top View RIN4 30 LIN3 31 RIN3 Power Supply 1.6 ∼ 3. [AK5702] ...

Page 64

... CSN CCLK 15 14 CDTI AK5702VN TDMIN 13 TEST 12 Top View 11 MCKO SDTOA 10 SDTOB Power Supply 1.6 ∼ 3.6V MIC Power Supply 2.4 ∼ 3.6V + CSN CDTI AK5702VN TDMIN 13 TEST 12 Top View 11 MCKO SDTOA 10 SDTOB Analog Ground Power Supply 1.6 ∼ 3. μP DSP Digital Ground [AK5702] 2007/06 ...

Page 65

Grounding and Power Supply Decoupling The AK5702 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from the system’s analog supply. If AVDD and DVDD are supplied separately, the power-up sequence is not ...

Page 66

Clock Set up When ADC is powered-up, the clocks must be supplied. 1. PLL Master Mode. Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:00H, D2) (4) MCKO bit (Addr:06H, D2) PMPLL bit (Addr:01H, D0) MCKI pin M/S ...

Page 67

PLL Slave Mode (LRCK or BCLK pin) Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:00H, D2) PMPLL bit (Addr:01H, D0) LRCK pin BCLK pin Internal Clock <Example> (1) After Power Up: PDN pin “L” → “H” “L” ...

Page 68

PLL Slave Mode (MCKI pin) Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:00H, D2) (4) MCKO bit (Addr:06H, D2) PMPLL bit (Addr:01H, D0) MCKI pin MCKO pin BCLK pin LRCK pin <Example> (1) After Power Up: PDN ...

Page 69

EXT Slave Mode Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:00H, D2) MCKI pin LRCK pin BCLK pin <Example> (1) After Power Up: PDN pin “L” → “H” “L” time of 150ns or more is needed to ...

Page 70

EXT Master Mode Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:00H, D2) MCKI pin M/S bit (Addr:01H, D1) TE3-0 bits "1010" (Addr:0DH, D7-4) TMASTER bit (Addr:0EH, D1) (4) BCLK pin LRCK pin <Example> (1) After Power Up: ...

Page 71

MIC Input Recording (Stereo) FS3-0 bits X,XXX (Addr:05H, D3-0) (1) MIC Control 0, 01 (Addr:02H, D4 (2) & Addr:03H, D1-0) Timer Control XXH (Addr:0AH) (3) ALC Control 1 XXH (Addr:0BH) (4) ALC Control 2 XXH (Addr:0CH) ALC State ALC ...

Page 72

Stop of Clock Master clock can be stopped when ADC is not used. 1. PLL Master Mode (1) PMPLL bit (Addr:01H, D0) M/S bit (Addr:01H, D1) (2) MCKO bit "H" or "L" (Addr:06H, D2) (3) External MCKI Input <Example> ...

Page 73

PLL Slave Mode (MCKI pin) (1) PMPLL bit (Addr:01H, D0) (2) MCKO bit (Addr:06H, D2) External MCKI Input <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop MCKO output: MCKO bit = “1” → “0” ...

Page 74

Power down If the clocks are supplied, power down VCOM (PMVCM bit: “1” → “0”) after all blocks except for VCOM are powered-down and a master clock stops. The AK5702 is also powered-down by PDN pin = “L”. When ...

Page 75

QFN (Unit: mm) 5.00 ± 0.10 4.75 ± 0. +0.07 0.23 -0.05 0.10 0.08 Note) The exposed pad on the bottom surface of the package must be open or connected to the ground. ■ ...

Page 76

Date (YY/MM/DD) Revision 07/06/07 00 These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized ...

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