AK4440 AKM [Asahi Kasei Microsystems], AK4440 Datasheet - Page 13

• Manufacturer Part Number: AK4440
• Description: 192kHz 24-Bit 8ch DAC with 2Vrms Output
• Manufacturer: AKM [Asahi Kasei Microsystems]

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In parallel control mode, the DIF0 and TDM0B pins as shown in
value of DIF0 and TDM0B bits are ignored. In serial control mode, the DIF2-0 and TDM1-0 bits shown in
select 11 serial data modes. Initial value of DIF2-0 bits is “010”. In all modes the serial data is MSB-first, 2’s
complement format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by
zeroing the unused LSBs.
In parallel control mode, when the TDM0B pin = “L”, the audio interface format is TDM256 mode
data of all DACs (eight channels) are input to the SDTI1 pin. The input data to SDTI2-4 pins are ignored. BICK should
be fixed to 256fs.
In serial control mode, when the TDM0 bit = “1” and the TDM1 bit = “0”, the audio interface format is TDM256 mode
(Table
pins are ignored. BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be at least 1/256fs. The audio
data is MSB-first, 2’s complement format. The input data to the SDTI1 pin is latched on the rising edge of BICK. In
TDM128 mode (TDM1-0 bits = “11”,
SDTI1 pin. The other four data (L3, R3, L4, R4) are input to the SDTI2 pin. The input data to SDTI3-4 pins are
ignored. BICK should be fixed to 128fs. The audio data is MSB-first, 2’s complement format. The input data to
SDTI1-2 pins are latched on the rising edge of BICK.
MS1088-E-01
TDM256
TDM128
Normal
Audio Serial Interface Format
Mode
8), and the audio data of all DACs (eight channels) are input to the SDTI1 pin. The input data to the SDTI2-4
TDM256
Normal
Mode
10
0
1
2
3
4
5
6
7
8
9
TDM1
2
3
5
6
Table 8. Audio Data Formats (Serial control mode) (N/A: Not available)
bit
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
TDM0B pin
TDM0
Table 7. Audio Data Formats (Parallel control mode)
bit
H
H
L
L
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Table
DIF2
bit
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
8), the audio data of DACs (four channels; L1, R1, L2, R2) are input to the
DIF0 pin
H
H
L
L
DIF1
bit
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
SDTI Format
24-bit MSB Justified
24-bit I
24-bit MSB Justified
24-bit I
- 13 -
DIF0
bit
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
2
2
S Compatible
S Compatible
SDTI Format
16-bit LSB Justified
20-bit LSB Justified
24-bit MSB Justified
24-bit I
24-bit LSB Justified
N/A
N/A
24-bit MSB Justified
24-bit I
24-bit LSB Justified
N/A
N/A
24-bit MSB Justified
24-bit I
24-bit LSB Justified
Table 7
2
2
2
S Compatible
S Compatible
S Compatible
can select four serial data modes. The register
LRCK
H/L
L/H
↑
↓
LRCK
BICK
H/L
H/L
H/L
L/H
H/L
≥48fs
≥48fs
256fs
256fs
↑
↓
↑
↑
↓
↑
(Table
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
256fs
256fs
256fs
128fs
128fs
128fs
Figure
Figure 8
Figure 9
Figure 10
Figure 11
7). The audio
Table 8
Figure
Figure 6
Figure 7
Figure 8
Figure 9
Figure 7
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
[AK4440]
2011/03
can