AK5357ET AKM [Asahi Kasei Microsystems], AK5357ET Datasheet - Page 13

• Manufacturer Part Number: AK5357ET
• Description: 24Bit 96kHz ?? ADC
• Manufacturer: AKM [Asahi Kasei Microsystems]

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The AK5357 is placed in the power-down mode by bringing the PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be executed after power-up. In the power-down mode, the VCOM is the same voltage as
AGND. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO
becomes available after 4129 cycles of LRCK clock in master mode or 4132 cycles of LRCK clock in slave mode. During
initialization, the ADC digital output data of both channels are forced to a 2’s complement “0”. The ADC outputs settle in
the value corresponding to the input signals after the initialization was completed (Settling approximately takes the group
delay time).
Notes:
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The AK5357 should be reset once by bringing the PDN pin “L” after power-up. In slave mode, the internal timing starts
clocking by the rising edge (falling edge at mode 1) of LRCK after exiting from reset and power down state by MCLK.
The AK5357 is power down state until LRCK is input. In master mode, the internal timing starts when MCLK is input.
MS0294-E-02
(1) 4132/fs in slave mode and 4129/fs in master mode.
(2) Digital output corresponding to analog input has the group delay (GD).
(3) A/D output is “0” data at the power-down state.
(4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5357 should be in the power-down state.
Power down
System Reset
Internal
A/D In
A/D Out
Clock In
MCLK,LRCK,SCLK
PDN
(Analog)
(Digital)
State
Normal Operation
Idle Noise
GD
Figure 3. Power-down/up sequence example
(2)
(4)
Power-down
“0”data
- 13 -
(3)
Initialize
“0”data
(1)
Idle Noise
Normal Operation
GD
[AK5357]
2007/11