AK4384VT AKM [Asahi Kasei Microsystems], AK4384VT Datasheet

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AK4384VT

Manufacturer Part Number
AK4384VT
Description
106dB 192kHz 24-Bit 2ch DAC
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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The AK4384 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit
architecture for its modulator the AK4384 delivers a wide dynamic range while preserving linearity for
improved THD+N performance. The AK4384 integrates a combination of SCF and CTF filters increasing
performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate
make this part ideal for a wide range of applications including DVD-Audio. The AK4384 is offered in a
space saving 16pin TSSOP package.
MS0176-E-00
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
LRCK
SDTI
BICK
Interface
o Sampling Rate Ranging from 8kHz to 192kHz
o 128 times Oversampling (Normal Speed Mode)
o 64 times Oversampling (Double Speed Mode)
o 32 times Oversampling (Quad Speed Mode)
o 24-Bit 8 times FIR Digital Filter
o SCF with High Tolerance to Clock Jitter
o 2nd order Analog LPF
o Single Ended Output Buffer
o Digital de-emphasis for 32k, 44.1k and 48kHz sampling
o Soft mute
o Digital Attenuator (Linear 256 steps)
o I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I
o Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
o THD+N: -94dB
o Dynamic Range: 106dB
o Power supply: 4.5 to 5.5V
o Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
Interface
Audio
Data
P/S
µP
PDN
ATT
ATT
GENERAL DESCRIPTION
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
De-emphasis
FEATURES
Interpolator
Interpolator
Control
106dB 192kHz 24-Bit 2ch
- 1 -
8X
8X
Modulator
Modulator
MCLK
Divider
Clock
SCF
SCF
LPF
LPF
AK4384
2
S
VDD
VSS
VCOM
DZFL
DZFR
AOUTR
AOUTL
DAC
2002/09

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AK4384VT Summary of contents

Page 1

The AK4384 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit architecture for its modulator the AK4384 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4384 integrates a combination ...

Page 2

... Ordering Guide AK4384VT -40 AKD4384 Evaluation Board for AK4384 n Pin Layout MCLK BICK SDTI LRCK PDN SMUTE/CSN ACKS/CCLK DIF0/CDTI No. Pin Name I/O 1 MCLK I 2 BICK I 3 SDTI I 4 LRCK I 5 PDN I 6 SMUTE I CSN I 7 ACKS I CCLK I 8 DIF0 I CDTI AOUTR ...

Page 3

ASAHI KASEI (VSS=0V; Note 1) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Ambient Operating Temperature Storage Temperature Note: 1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may results in ...

Page 4

C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz 20kHz; R Parameter Resolution Dynamic Characteristics THD+N fs=44.1kHz BW=20kHz fs=96kHz BW=40kHz fs=192kHz BW=40kHz Dynamic Range (-60dBFS with A-weighted) S/N (A-weighted) Interchannel Isolation (1kHz) Interchannel Gain Mismatch DC Accuracy ...

Page 5

ASAHI KASEI SHARP ROLL-OFF FILTER CHARACTERISTICS ( VDD = 4.5 5.5V 44.1kHz; DEM = OFF; SLOW = “0”) Parameter Digital filter Passband 0.05dB (Note 9) -6.0dB Stopband (Note 9) Passband Ripple Stopband Attenuation Group Delay ...

Page 6

ASAHI KASEI (Ta=25 C; VDD=4.5 5.5V; C =20pF) L Parameter Master Clock Frequency Duty Cycle LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle Audio Interface Timing BICK Period Normal Speed Mode Double/Quad Speed Mode BICK ...

Page 7

ASAHI KASEI n Timing Diagram MCLK tCLKH LRCK BICK tBCKH LRCK tBLR BICK SDTI MS0176-E-00 1/fCLK tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs tBCK tBCKL Clock Timing tLRB tSDS tSDH Serial Interface Timing - 7 - [AK4384] VIH VIL ...

Page 8

ASAHI KASEI CSN tCSS CCLK CDTI C1 CSN CCLK CDTI D3 PDN MS0176-E-00 tCCKL tCCKH tCDS tCDH C0 R/W WRITE Command Input Timing WRITE Data Input Timing tPD Power-down Timing - 8 - [AK4384] VIH VIL VIH ...

Page 9

ASAHI KASEI n System Clock The external clocks, which are required to operate the AK4384, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to ...

Page 10

ASAHI KASEI LRCK fs 176.4kHz 192.0kHz Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode) Table 5. Sampling Speed (Auto Setting Mode: Default) LRCK fs 128fs 192fs 32.0kHz - - 44.1kHz - - 48.0kHz - - 88.2kHz - ...

Page 11

LRCK BICK (32fs) SDTI Mode BICK (64fs) SDTI Don’t care Mode 0 15:MSB, 0:LSB Lch Data LRCK BICK (64fs) SDTI Don’t care Mode 1 19:MSB, ...

Page 12

LRCK BICK (64fs) SDTI 23 22 23:MSB, 0:LSB n De-emphasis Filter A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled with DEM0 and DEM1. ...

Page 13

ASAHI KASEI n Zero Detection The AK4384 has channel-independent zeros detect function. When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately ...

Page 14

System Reset The AK4384 should be reset once by bringing PDN= “L” upon power-up. The AK4384 is powered up and the internal timing starts clocking by LRCK “ ” after exiting reset and power down state by MCLK. The ...

Page 15

ASAHI KASEI n Reset Function When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZFL/DZFR pins go to “H”. Figure 7 shows the example of reset by ...

Page 16

ASAHI KASEI n Mode Control Interface Some function of the AK4384 can be controlled by pins (parallel control mode) shown in Table 11. The serial control interface is enabled by the P/S pin = “L”. Internal registers may be written ...

Page 17

ASAHI KASEI n Register Definitions Addr Register Name D7 00H Control 1 ACKS default 1 RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation When MCLK frequency or DFS changes, the AK4384 should be ...

Page 18

ASAHI KASEI DZFM: Data Zero Detect Mode 0: Channel Separated Mode 1: Channel ANDed Mode If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both channels ...

Page 19

ASAHI KASEI Figure 9 and 10 show the system connection diagram. An evaluation board (AKD4384) is available in order to allow an easy study on the layout of a surrounding circuit. Master Clock 64fs 24bit Audio Data fs Reset & ...

Page 20

ASAHI KASEI 1. Grounding and Power Supply Decoupling VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor, especially 0.1 F ceramic capacitor for high frequency should be placed as near to ...

Page 21

TSSOP (Unit: mm) *5.0 0 0.22 0.1 0.13 M Seating Plane NOTE: Dimension "*" does not include mold flash. n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0176-E-00 PACKAGE ...

Page 22

These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability for infringement ...

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