AK4388A AKM [Asahi Kasei Microsystems], AK4388A Datasheet
AK4388A
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AK4388A Summary of contents
Page 1
... THD+N performance. The AK4388A integrates a combination of SCF and CTF filters increasing performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate make this part ideal for a wide range of applications including DVD-Audio. The AK4388A is offered in a space saving 16pin TSSOP package. ...
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... Ordering Guide AK4388AET AKD4388A Evaluation Board for the AK4388A ■ Pin Layout MCLK BICK SDTI LRCK RSTN SMUTE ACKS DIF0 ■ Compatibility with AK4384, AK4388 1. Function Functions THD+N Output Voltage Slow Roll-Off Filter Mode Setting DEM in Parallel control Audio Format in Parallel control ...
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... Audio Serial Data Clock Pin Audio Serial Data Input Pin L/R Clock Pin Reset Mode Pin When at “L”, the AK4388A is in power-down mode and is held in reset. The AK4388A must always be reset upon power-up. Soft Mute Pin “H”: Enable, “L”: Disable Auto Setting Mode Pin “ ...
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... Note 7. The DIF1 pin is held to VDD and the other all digital inputs including clock pins (MCLK, BICK and LRCK) are held to VSS. MS1008-E-02 ANALOG CHARACTERISTICS min (Note 2) 0dBFS –60dBFS 0dBFS –60dBFS 0dBFS –60dBFS (Note 3) 98 (Note (Note 5) 2.95 (Note 6) 5 (Note [AK4388A] typ max Units 24 Bits –90 –80 dB – – – – – 106 dB 106 dB 100 dB 0 ...
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... Note 9. Calculated delay time caused by digital filter. This time is measured from setting the 16/24bit data of both channels to input register to the output of the analog signal. MS1008-E-02 FILTER CHARACTERISTICS Symbol min 24 fs=44.1kHz FR - fs=96kHz FR - fs=192kHz [AK4388A] typ max Units 20.0 kHz 22.05 - kHz kHz ± 0. 19.3 - 1/fs - –1.5 –0.2/+0 0/+0.6 dB ±0 ±0 ...
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... SDTI Hold Time SDTI Setup Time Reset Timing RSTN Pulse Width Note 11. BICK rising edge must not occur at the same time as LRCK edge. Note 12. The AK4388A can be reset by bringing RSTN pin = “L” → “H”. MS1008-E-02 DC CHARACTERISTICS Symbol min VIH 2 ...
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... BICK SDTI RSTN MS1008-E-02 1/fCLK tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs tBCK tBCKL Figure 1. Clock Timing tLRB tSDS tSDH Figure 2. Serial Interface Timing tRST Figure 3. Power-down Timing - 7 - [AK4388A] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIL 2010/09 ...
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... System Clock The external clocks, which are required to operate the AK4388A, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS pin = “ ...
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... Don’t care Figure 4. Mode 0 Timing Don’t care Figure 5. Mode 1 Timing - 9 - [AK4388A] Table 5 can select four serial BICK Figure ≥32fs Figure 4 ≥48fs Figure 5 ≥48fs Figure 6 ≥48fs or 32fs Figure ...
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... Don’t care 23 Lch Data Figure 7. Mode 3 Timing DEM pin De-emphasis Filter OFF - Don’t care Rch Data Don’t care Rch Data (default) [AK4388A 2010/09 ...
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... When the input data at both channels are continuously zeros for 8192 LRCK cycles, the DZF pin goes to “H”. The DZF pin immediately returns to “L” if input data are not zero. MS1008-E-02 1024/fs (1) GD (2) (4) 8192/fs Figure 8. Soft Mute and Zero Detection - 11 - [AK4388A] (Figure 8). 1024/fs (3) GD 2010/09 ...
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... System Reset The AK4388A must be reset once by bringing the RSTN pin = “L” upon power-up. The AK4388A is powered up and the internal timing starts clocking by LRCK “↑” after exiting reset by MCLK. The AK4388A is in reset state until LRCK is input. ...
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... Reset Function (MCLK, LRCK or BICK stop) When the MCLK, LRCK or BICK stops, the digital circuit of the AK4388A is placed in power-down mode. When the MCLK, LRCK and BICK are restarted, power-down mode is released and the AK4388A returns to normal operation mode. RSTN pin ...
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... All input pins except DIF1 and DEM pins must not be left floating. MS1008-E-02 SYSTEM DESIGN 1 MCLK BICK 2 SDTI 3 4 LRCK AK4388A 5 RSTN SMUTE 6 ACKS 7 8 DIF0 Analog Ground Figure 11. Typical Connection Diagram - 14 - [AK4388A] Optional External Mute Circuits DZF 16 DEM 15 Analog VDD 14 + Supply 5V 10u 0.1u VSS 13 10u + VCOM 12 Lch Out AOUTL 11 ...
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... LPF Circuit Example (simple) 390p 3.9k 3.3k +Vop 2.7k 3.9k -Vop 390p fc=125.8kHz, Q=0.752, g=0.058dB at 40kHz nd order LPF Circuit Example (using op-amp with dual power supplies [AK4388A] Figure 13 shows an Analog Out 3.2Vpp (1.13Vrms) Analog Out 5.93Vpp (2.09Vrms) 2010/09 ...
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... Seating Plane NOTE: Dimension "*" does not include mold flash. ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS1008-E-02 PACKAGE 9 8 0.65 Detail A 0.10 Epoxy Cu Solder (Pb free) plate - 16 - [AK4388A] 1.1 (max) A 0.17±0.05 0.1±0.1 0-10° 2010/09 ...
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... Date (YY/MM/DD) Revision 08/09/19 00 08/10/17 01 10/09/28 02 MS1008-E-02 MARKING (AK4388AET) AKM 4388AET XXYYY Pin #1 indication 1) Date Code : XXYYY (5 digits) 2) XX: Lot# YYY: Date Code Marketing Code : 4388AET 3) Asahi Kasei Logo 4) REVISION HISTORY Reason Page Contents First Edition Description 10 ■ De-emphasis Filter Addition “In case of double speed and quad speed mode, the digital de-emphasis filter is always off.” ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1008-E-02 IMPORTANT NOTICE , and AKM assumes no responsibility for such use, except for the use Note2 [AK4388A] in any safety, life support, or Note1) 2010/09 ...