AK4393VM AKM [Asahi Kasei Microsystems], AK4393VM Datasheet

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AK4393VM

Manufacturer Part Number
AK4393VM
Description
Advanced Multi-Bit 96kHz 24-Bit ?? DAC
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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The AK4393 is a high performance stereo DAC for the 96kHz sampling mode of DAT, DVD including a
24bit digital filter. The AK4393 introduces the advanced multi-bit system for ΔΣ modulator. This new
architecture achieves the wider dynamic range, while keeping much the same superior distortion
characteristics as conventional Single-Bit way. In the AK4393, the analog outputs are filtered in the
analog domain by switched-capacitor filter (SCF) with high tolerance to clock jitter. The analog outputs
are full differential output, so the device is suitable for hi-end applications. The operating voltages support
analog 5V and digital 3.3V, so it is easy to I/F with 3.3V logic IC.
M0039-E-03
SMUTE
SDATA
LRCK
BICK
PDN
DFS
DIF0
Control Register
CSN
De-emphasis
De-emphasis
Audio Data
Soft Mute
Soft Mute
• 128x Oversampling
• Sampling Rate up to 108kHz
• 24Bit 8x Digital Filter
• High Tolerance to Clock Jitter
• Low Distortion Differential Output
• Digital de-emphasis for 32, 44.1, 48 & 96kHz sampling
• Soft Mute
• THD+N: -100dB
• DR, S/N: 120dB
• I/F format:
• Master Clock:
• Power Supply: 4.75 to 5.25V (Analog), 3 to 5.25V (Digital)
• Small Package: 28pin SSOP
Interface
DIF1
CCLK
Ripple: ±0.005dB, Attenuation: 75dB
DIF2
CDTI
Advanced Multi-Bit 96kHz 24-Bit ΔΣ DAC
GENERAL DESCRIPTION
DVDD
P/S
Interpolator
Interpolator
MSB justified, 16/20/24bit LSB justified, I
Normal Speed: 256fs, 384fs, 512fs or 768fs
Double Speed: 128fs, 192fs, 256fs or 384fs
MCLK
FEATURES
8x
8x
DVSS
- 1 -
Clock Divider
CKS0
De-emphasis
DEM0
Modulator
CKS1
Modulator
Control
ΔΣ
ΔΣ
DEM1
CKS2 VREFH VREFL
AVDD
SCF
SCF
AVSS
AK4393
2
S
BVSS
AOUTL+
AOUTL-
AOUTR+
VCOM
AOUTR-
[AK4393]
2012/01

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AK4393VM Summary of contents

Page 1

The AK4393 is a high performance stereo DAC for the 96kHz sampling mode of DAT, DVD including a 24bit digital filter. The AK4393 introduces the advanced multi-bit system for ΔΣ modulator. This new architecture achieves the wider dynamic range, while ...

Page 2

... Ordering Guide -40 ~ +85 °C AK4393VM Pin Layout DVSS DVDD MCLK PDN BICK SDATA LRCK SMUTE/CSN DFS DEM0/CCLK DEM1/CDTI DIF0 DIF1 DIF2 M0039-E-03 28pin SSOP (0.65mm pitch Top View [AK4393] 28 CKS2 27 CKS1 26 CKS0 P VCOM ...

Page 3

No. Pin Name I/O 1 DVSS - 2 DVDD - 3 MCLK I PDN I 4 BICK I 5 SDATA LRCK I SMUTE I 8 CSN I DFS I 9 DEM0 I 10 CCLK I DEM1 I ...

Page 4

BVSS, DVSS = 0V; Note 1) Parameter Power Supplies: Analog Digital | BVSS-DVSS | Input Current , Any pin Except Supplies Input Voltage Ambient Operating Temperature Storage Temperature Notes: 1. All voltages with respect to ground. 2. AVSS, BVSS ...

Page 5

AVDD = 5V, DVDD = 3.3V; AVSS, BVSS, DVSS = 0V, VREFH = AVDD, VREFL = AVSS 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement Bandwidth = 20Hz~20kHz; ≥ 600Ω; External ...

Page 6

FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V 44.1kHz; Normal Speed Mode; DEM = OFF) Parameter Digital Filter ±0.01dB Passband (Note 14) -6.0dB Stopband (Note 14) Passband Ripple Stopband Attenuation Group Delay ...

Page 7

AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; C Parameter Master Clock Timing Normal Speed: 256fs, Double Speed: 128fs Pulse Width Low Pulse Width High Normal Speed: 384fs, Double Speed: 192fs Pulse Width Low Pulse Width High Normal Speed: ...

Page 8

Timing Diagram MCLK tCLKH LRCK BICK tBCKH For Double Speed mode timing please see Appendix A for relationship of MCLK and BCLK/LRCK. LRCK tBLR BICK SDATA M0039-E-03 1/fCLK tCLKL 1/fns,1/fds tBCK tBCKL Clock Timing tLRB tSDS tSDH Audio Interface Timing ...

Page 9

CSN tCSS CCLK CDTI C1 CSN CCLK CDTI D3 PDN M0039-E-03 tCCKL tCCKH tCDS tCDH C0 R/W WRITE Command Input Timing D2 D1 WRITE Data Input Timing tPW Power-down Timing - 9 - [AK4393] 50%DVDD 50%DVDD A4 50%DVDD tCSW 50%DVDD ...

Page 10

System Clock The external clocks, which are required to operate the AK4393, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. However, in Double Speed Mode, the phase relationship ...

Page 11

Audio Serial Interface Format Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the DIF0-2 as shown in Table 5. In all formats the serial data is MSB-first, ...

Page 12

LRCK BICK (64fs) SDATA 23 22 23:MSB, 0:LSB Lch Data LRCK BICK (64fs) SDATA 23 22 23:MSB, 0:LSB De-emphasis filter A digital de-emphasis filter is available for 32, 44. 96kHz ...

Page 13

Soft mute operation Soft mute operation is performed at digital domain. When SMUTE goes to “H”, the output signal is attenuated by -∞ during 1024 LRCK cycles. When SMUTE is returned to “L”, the mute is cancelled and the output ...

Page 14

System Reset The AK4393 should be reset once by bringing PDN = “L” upon power-up. The AK4393 is powered up and the internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4393 ...

Page 15

Mode Control Interface Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4393. For DIF2-0, CKS2-0 and DFS, the setting of pin and register are “ORed” internally. So, even serial control mode, pin setting ...

Page 16

Register Map Addr Register Name D7 00H Control 1 0 01H Control 2 0 02H Test TEST7 Notes: For addresses from 03H to 1FH, data must not be written. When PDN pin goes to “L”, the registers are initialized to ...

Page 17

Figure 8 and 9 show the system connection diagram. An evaluation board (AKD4393) is available which demonstrates the optimum layout, power supply arrangements and measurement results. Master Clock Reset & Power down 64fs 24bit Audio Data fs Micro- controller Digital ...

Page 18

Master Clock Reset & Power down 64fs 24bit Audio Data fs Mode setting Digital Ground Analog Ground Figure 9. Typical Connection Diagram (Parallel mode) Notes: - LRCK = fs, BICK = 64fs. - Power lines of AVDD and DVDD should ...

Page 19

Grounding and Power Supply Decoupling To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively. AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. If ...

Page 20

AOUTL 300 10n 4 NJM5534D 220 10n 47u AOUTL 300 300 4 10n NJM5534D 220 M0039-E-03 + 10u 0.1u 6 10u + 0. ...

Page 21

SSOP (Unit: mm) 10.40MAX 28 1 0.32±0.08 Seating Plane NOTE: Dimension "*" does not include mold flash. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: M0039-E-03 PACKAGE 15 14 0.65 Detail A 0.10 ...

Page 22

... Double Speed Mode, the phase relationship between MCLK and LRCK/BICK is limited. (Refer to Appendix A).” → Added “Appendix A” → Added AK4393VF was deleted. (28pin VSOP) 21, 22 AK4393VM was added. (28pin SSOP) Ordering Guide was changed. PACKAGE was changed. MARKING was changed [AK4393] 2012/01 ...

Page 23

These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status ...

Page 24

In Double Speed Mode, the phase relationship between MCLK and LRCK/BICK is limited (Table 7). If the phase relationship happens during this prohibited period possible to occur the inverse of output channel. The phase relationship must be set ...

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