AK4393VM AKM [Asahi Kasei Microsystems], AK4393VM Datasheet
AK4393VM
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AK4393VM Summary of contents
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The AK4393 is a high performance stereo DAC for the 96kHz sampling mode of DAT, DVD including a 24bit digital filter. The AK4393 introduces the advanced multi-bit system for ΔΣ modulator. This new architecture achieves the wider dynamic range, while ...
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... Ordering Guide -40 ~ +85 °C AK4393VM Pin Layout DVSS DVDD MCLK PDN BICK SDATA LRCK SMUTE/CSN DFS DEM0/CCLK DEM1/CDTI DIF0 DIF1 DIF2 M0039-E-03 28pin SSOP (0.65mm pitch Top View [AK4393] 28 CKS2 27 CKS1 26 CKS0 P VCOM ...
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No. Pin Name I/O 1 DVSS - 2 DVDD - 3 MCLK I PDN I 4 BICK I 5 SDATA LRCK I SMUTE I 8 CSN I DFS I 9 DEM0 I 10 CCLK I DEM1 I ...
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BVSS, DVSS = 0V; Note 1) Parameter Power Supplies: Analog Digital | BVSS-DVSS | Input Current , Any pin Except Supplies Input Voltage Ambient Operating Temperature Storage Temperature Notes: 1. All voltages with respect to ground. 2. AVSS, BVSS ...
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AVDD = 5V, DVDD = 3.3V; AVSS, BVSS, DVSS = 0V, VREFH = AVDD, VREFL = AVSS 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement Bandwidth = 20Hz~20kHz; ≥ 600Ω; External ...
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FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta = 25°C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V 44.1kHz; Normal Speed Mode; DEM = OFF) Parameter Digital Filter ±0.01dB Passband (Note 14) -6.0dB Stopband (Note 14) Passband Ripple Stopband Attenuation Group Delay ...
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AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; C Parameter Master Clock Timing Normal Speed: 256fs, Double Speed: 128fs Pulse Width Low Pulse Width High Normal Speed: 384fs, Double Speed: 192fs Pulse Width Low Pulse Width High Normal Speed: ...
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Timing Diagram MCLK tCLKH LRCK BICK tBCKH For Double Speed mode timing please see Appendix A for relationship of MCLK and BCLK/LRCK. LRCK tBLR BICK SDATA M0039-E-03 1/fCLK tCLKL 1/fns,1/fds tBCK tBCKL Clock Timing tLRB tSDS tSDH Audio Interface Timing ...
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CSN tCSS CCLK CDTI C1 CSN CCLK CDTI D3 PDN M0039-E-03 tCCKL tCCKH tCDS tCDH C0 R/W WRITE Command Input Timing D2 D1 WRITE Data Input Timing tPW Power-down Timing - 9 - [AK4393] 50%DVDD 50%DVDD A4 50%DVDD tCSW 50%DVDD ...
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System Clock The external clocks, which are required to operate the AK4393, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. However, in Double Speed Mode, the phase relationship ...
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Audio Serial Interface Format Data is shifted in via the SDATA pin using BICK and LRCK inputs. Five data formats are supported and selected by the DIF0-2 as shown in Table 5. In all formats the serial data is MSB-first, ...
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LRCK BICK (64fs) SDATA 23 22 23:MSB, 0:LSB Lch Data LRCK BICK (64fs) SDATA 23 22 23:MSB, 0:LSB De-emphasis filter A digital de-emphasis filter is available for 32, 44. 96kHz ...
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Soft mute operation Soft mute operation is performed at digital domain. When SMUTE goes to “H”, the output signal is attenuated by -∞ during 1024 LRCK cycles. When SMUTE is returned to “L”, the mute is cancelled and the output ...
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System Reset The AK4393 should be reset once by bringing PDN = “L” upon power-up. The AK4393 is powered up and the internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4393 ...
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Mode Control Interface Pins (parallel control mode) or registers (serial control mode) can control each functions of the AK4393. For DIF2-0, CKS2-0 and DFS, the setting of pin and register are “ORed” internally. So, even serial control mode, pin setting ...
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Register Map Addr Register Name D7 00H Control 1 0 01H Control 2 0 02H Test TEST7 Notes: For addresses from 03H to 1FH, data must not be written. When PDN pin goes to “L”, the registers are initialized to ...
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Figure 8 and 9 show the system connection diagram. An evaluation board (AKD4393) is available which demonstrates the optimum layout, power supply arrangements and measurement results. Master Clock Reset & Power down 64fs 24bit Audio Data fs Micro- controller Digital ...
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Master Clock Reset & Power down 64fs 24bit Audio Data fs Mode setting Digital Ground Analog Ground Figure 9. Typical Connection Diagram (Parallel mode) Notes: - LRCK = fs, BICK = 64fs. - Power lines of AVDD and DVDD should ...
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Grounding and Power Supply Decoupling To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively. AVDD is supplied from analog supply in system and DVDD is supplied from digital supply in system. If ...
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AOUTL 300 10n 4 NJM5534D 220 10n 47u AOUTL 300 300 4 10n NJM5534D 220 M0039-E-03 + 10u 0.1u 6 10u + 0. ...
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SSOP (Unit: mm) 10.40MAX 28 1 0.32±0.08 Seating Plane NOTE: Dimension "*" does not include mold flash. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: M0039-E-03 PACKAGE 15 14 0.65 Detail A 0.10 ...
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... Double Speed Mode, the phase relationship between MCLK and LRCK/BICK is limited. (Refer to Appendix A).” → Added “Appendix A” → Added AK4393VF was deleted. (28pin VSOP) 21, 22 AK4393VM was added. (28pin SSOP) Ordering Guide was changed. PACKAGE was changed. MARKING was changed [AK4393] 2012/01 ...
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These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status ...
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In Double Speed Mode, the phase relationship between MCLK and LRCK/BICK is limited (Table 7). If the phase relationship happens during this prohibited period possible to occur the inverse of output channel. The phase relationship must be set ...