LFEC LATTICE [Lattice Semiconductor], LFEC Datasheet - Page 22

• Manufacturer Part Number: LFEC
• Description: LatticeECP/EC Family Data Sheet
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Table 2-8. An Example of Sign Extension
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two
unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and
overflow signal is indicated. When two positive numbers are added with a negative sum and when two negative
numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and an overflow
signal is indicated. Note when overflow occurs the overflow flag is present for only one cycle. By counting these
overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow signal for signed
and unsigned operands are listed in Figure 2-22.
Figure 2-22. Accumulator Overflow/Underflow Conditions
ispLEVER Module Manager
The user can access the sysDSP block via the ispLEVER Module Manager, which has options to configure each
DSP module (or group of modules) or through direct HDL instantiation. Additionally Lattice has partnered Math-
works to support instantiation in the Simulink tool, which is a Graphical Simulation Environment. Simulink works
with ispLEVER and dramatically shortens the DSP design cycle in Lattice FPGAs.
Number Unsigned
+5
-6
0101
0110
Overflow signal is generated
for one cycle when this
boundary is crossed
000000101
000000110
Unsigned
9-bit
000000000000000101
000000000000000110
0101111100
0101111110
0101111111
0101111100
0101111101
0101111110
0101111111
1010000010
0101111101
1010000000
1010000001
1010000010
1010000000
1010000001
Unsigned
18-bit
Unsigned Operation
Signed Operation
256
257
258
255
256
255
254
252
253
254
255
252
253
254
2-19
Signed
0101
1010
111111101
111111110
111111101
000000011
000000001
111111111
111111110
000000011
000000010
000000001
000000000
111111111
000000010
000000000
Two’s Complement
Signed 9-Bits
LatticeECP/EC Family Data Sheet
000000101
111111010
+3
+2
+1
-1
-2
-3
511
510
509
0
3
2
1
0
Carry signal is generated for
boundary is crossed
one cycle when this
000000000000000101
111111111111111010
Two’s Complement
Signed 18-bits
Architecture