LFEC LATTICE [Lattice Semiconductor], LFEC Datasheet - Page 33

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LFEC

Manufacturer Part Number
LFEC
Description
LatticeECP/EC Family Data Sheet
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet

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Lattice Semiconductor
options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain.
Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS,
BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards
(together with their supply and reference voltages) supported by the LatticeECP/EC devices. For further informa-
tion on utilizing the sysIO buffer to support a variety of standards please see the details of additional technical infor-
mation at the end of this data sheet.
Table 2-13. Supported Input Standards
Single Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI
HSTL18 Class I, II
HSTL18 Class III
HSTL15 Class I
HSTL15 Class III
SSTL3 Class I, II
SSTL2 Class I, II
SSTL18 Class I
Differential Interfaces
Differential SSTL18 Class I
Differential SSTL2 Class I, II
Differential SSTL3 Class I, II
Differential HSTL15 Class I, III
Differential HSTL18 Class I, II, III
LVDS, LVPECL, BLVDS, RSDS
1. When not specified V
2. JTAG inputs do not have a fixed threshold option and always follow V
Input Standard
2
2
2
CCIO
can be set anywhere in the valid operating range.
V
REF
2-30
1.08
0.75
1.25
0.9
0.9
1.5
0.9
(Nom.)
CCJ.
LatticeECP/EC Family Data Sheet
V
CCIO
1.8
1.5
3.3
1
(Nom.)
Architecture

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