A54SX08-1BG208 ETC1 [List of Unclassifed Manufacturers], A54SX08-1BG208 Datasheet

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A54SX08-1BG208

Manufacturer Part Number
A54SX08-1BG208
Description
54SX Family FPGAs
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
54SX Family FPGAs
Le a di ng E dg e P er f or m a nc e
• 320 MHz Internal Performance
• 3.7 ns Clock-to-Out (Pin-to-Pin)
• 0.1 ns Input Set-Up
• 0.25 ns Clock Skew
Sp e ci f ic at ion s
• 12,000 to 48,000 System Gates
• Up to 249 User-Programmable I/O Pins
• Up to 1080 Flip-Flops
• 0.35µ CMOS
S X P r od u c t P ro fi l e
J u n e 2 0 0 3
© 2003 Actel Corporation
Capacity
Logic Modules
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
JTAG
PCI
Clock-to-Out
Input Set-Up (External)
Speed Grades
Temperature Grades
Packages (by pin count)
Typical Gates
System Gates
Combinatorial Cells
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
Std, –1, –2, –3
A54SX08
144, 176
12,000
C, I, M
3.7 ns
0.8 ns
8,000
768
512
256
130
Yes
208
100
144
84
3
F ea t u r es
• 66 MHz PCI
• CPLD and FPGA Integration
• Single Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3V Operation with 5.0V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug capability with
• Boundary Scan Testing in Compliance with IEEE Standard
• Secure Programming Technology Prevents Reverse
Std, –1, –2, –3
A54SX16
Silicon Explorer II
1149.1 (JTAG)
Engineering and Design Theft
16,000
24,000
C, I, M
3.9 ns
0.5 ns
1,452
924
528
175
Yes
208
100
176
3
Std, –1, –2, –3
A54SX16P
144, 176
16,000
24,000
C, I, M
4.4 ns
0.5 ns
1,452
924
528
175
Yes
Yes
208
100
3
Std, –1, –2, –3
A54SX32
144, 176
313, 329
32,000
48,000
C, I, M
4.6 ns
0.1 ns
2,880
1,080
1800
249
208
Yes
3
v 3 . 1
1

Related parts for A54SX08-1BG208

A54SX08-1BG208 Summary of contents

Page 1

... Deterministic, User-Controllable Timing • Unique In-System Diagnostic and Debug capability with Silicon Explorer II • Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) • Secure Programming Technology Prevents Reverse Engineering and Design Theft A54SX08 A54SX16 8,000 16,000 12,000 24,000 768 ...

Page 2

... A54SX16 P – Blank = Not PCI Compliant Part Number A54SX08 A54SX16 A54SX16P = 24,000 System Gates A54SX32 2 machines, and datapath logic. The general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or I/O module ...

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... A54SX08 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) 144-Pin Thin Quad Flat Pack (TQFP) 144-Pin Fine Pitch Ball Grid Array (FBGA) 176-Pin Thin Quad Flat Pack (TQFP) ...

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The SX family architecture was designed to satisfy next-generation performance and integration requirements for production-volume designs in a broad range of applications. ...

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The C-cell implements a range of combinatorial functions up to 5-inputs (Figure 3). Inclusion of the DB input and its associated inverter function dramatically increases the ...

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R-Cell Routed S1 Data Input S0 Direct Connect Input HCLK CLKA, CLKB, Internal Logic CKS CKP Cluster 1 Type 1 SuperCluster Figure 4 • Cluster Organization Clusters and SuperClusters can ...

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Technology Actel’s SX family is ...

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... The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM), making it the lowest-power architecture on the market. Table 1 • Supply Voltages Maximum Tolerance CCA CCI CCR A54SX08 A54SX16 3.3V 3.3V 5.0V A54SX32 3.3V 3.3V 3.3V A54SX16-P 3.3V 3.3V 5.0V 3.3V 5 ...

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The Silicon Explorer ...

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... Symbol Parameter Supply Voltage –0.3 to +6.0 CCR Supply Voltage –0.3 to +4.0 CCA DC Supply Voltage 2 V (A54SX08, A54SX16, –0.3 to +4.0 CCI A54SX32) DC Supply Voltage 2 V –0.3 to +6.0 CCI (A54SX16P) V Input Voltage –0 Output Voltage –0.5 to +3.6 ...

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...

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A54SX16P AC Specifications for (PCI Operation) Symbol Parameter I Switching Current High OH(AC) (Test Point) I Switching Current High OL(AC) (Test Point) I Low Clamp Current CL slew Output Rise Slew Rate R slew Output Fall Slew Rate F Notes: ...

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Figure 8 shows the 5.0V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P family. 0.50 0.45 0.40 0.35 0.30 0.25 ...

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Symbol ...

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54SX16P AC Specifications (3.3V PCI Operation) Symbol Parameter Condition 0 < V 0.3V Switching Current High I 0.7V OH(AC) (Test Point Switching Current ...

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Figure 9 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P family. 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.05 PCI I OH Minimum –0.10 –0.15 –0.20 Figure ...

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... A54SX08, A54SX16, A54SX32 5.0V First 3.3V Second 3.3V 3.3V First 5.0V Second A54SX16P 3.3V 3.3V Only 5.0V First 3.3V Second 3.3V 3.3V First 5.0V Second 5.0V First 3.3V Second 5.0V 3.3V First 5.0V Second V Power-Down Sequence CCI A54SX08, A54SX16, A54SX32 5.0V First 3.3V Second 3.3V 3.3V First 5.0V Second A54SX16P 3.3V 3.3V Only 5.0V First 3.3V Second 3.3V 3.3V First 5.0V Second 5.0V First 3.3V Second 5.0V 3.3V First 5.0V Second v3.1 Comments No possible damage to device. ...

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... Input Buffer EQO L p Output Buffer * EQCR RCLKA * EQCR RCLKB * EQHV s1 EQHF s1 HCLK clock array clock clock clock clock pF A54SX08 A54SX16 A54SX16P A54SX32 4.0 4.0 4.0 3.4 3.4 3.4 4.7 4.7 4.7 1.6 1.6 1.6 0.615 0.615 0.615 0.615 140 87 138 138 171 87 138 138 171 + ( ...

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...

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Step #2: Calculate Dynamic Power Consumption V *V CCA CCA m EQM n EQI p*f *( EQO L 0.5*( )+( EQCR 0.5*( )+(r ...

Page 21

The temperature that you select in Designer Series software ...

Page 22

... Clock t = 1.5 ns (100% Load) RCKH F = 250 MHz MAX Hard-Wired Clock t = 1.0 ns HCKH F = 320 MHz HMAX *Values shown for A54SX08-3, worst-case commercial conditions External Set- INY IRD1 SUD = 1.5 + 0.3 + 0.5 – 1.0 = 1.3 ns Clock-to-Out (Pin-to-Pin HCKH RCO = 1 ...

Page 23

GND 50% 50 ...

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SUD CLK Q CLR ...

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(Worst-Case ...

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(Worst-Case Commercial Conditions) Parameter Description Dedicated (Hard-Wired) Array Clock Network t Input LOW to ...

Page 27

(Worst-Case ...

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(Worst-Case Commercial Conditions) Parameter Description Dedicated (Hard-Wired) Array Clock Network t Input LOW to ...

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...

Page 30

(Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hard-Wired) Array Clock Network t Input LOW ...

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...

Page 32

(Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module ...

Page 33

(Worst-Case ...

Page 34

CLKA/B Clock A and B These pins are 3.3V/5.0V PCI/TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If ...

Page 35

...

Page 36

... TDI, I/O 54 I/O 55 I/O 56 I/O 57 TMS 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 GND CCI I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 PRB, I CCA GND 84 v3 A54SX08 Function V CCR I/O HCLK I/O I/O I/O I/O I/O I/O TDO, I/O I/O I/O I/O I/O I/O I/O V CCA V CCI GND I/O I/O I/O I/O I/O I/O V CCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB ...

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...

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... V V CCA CCA 42 I/O I/O 43 I/O I/O 44 I/O I/O 45 I/O I/O 46 I/O I/O 47 I/O I I/O 49 I/O I I/O 51 I/O I/O 52 GND GND 53 I/O I/O * Please note that Pin 65 in the A54SX32—PQ208 connect (NC). 38 A54SX32 A54SX08 Function Pin Number Function GND 54 TDI, I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 TMS 64 V 65* CCI I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 ...

Page 39

... I/O I/O 150 I/O I/O 151 I/O I/O 152 I/O I/O 153 I/O I/O 154 I/O I/O 155 NC I/O 156 NC I/O 157 GND GND * Please note that Pin 65 in the A54SX32—PQ208 connect (NC). A54SX32 A54SX08 Function Pin Number Function I/O 158 I/O 159 I/O 160 I/O 161 I/O 162 I/O 163 I/O 164 V 165 CCA V 166 CCI I/O 167 I/O 168 I/O 169 ...

Page 40

144 1 40 (continued) 144-Pin TQFP v3 ...

Page 41

... I/O 27 I/O I/O 28 GND GND CCI CCI CCA CCA 31 I/O I/O 32 I/O I/O 33 I/O I/O 34 I/O I/O 35 I/O I/O 36 GND GND 37 I/O I/O 38 I/O I/O 39 I/O I/O 40 I/O I/O A54SX32 A54SX08 Function Pin Number Function GND 41 TDI, I/O 42 I I/O 45 I/O 46 I/O 47 I/O 48 TMS CCI GND 51 I/O 52 I/O 53 I/O 54 PRB, I/O I I/O 57 GND I CCR ...

Page 42

... V CCI CCI 103 I/O I/O 104 I/O I/O 105 I/O I/O 106 I/O I/O 107 I/O I/O 108 I/O I/O 109 GND GND 110 I/O I/O 111 I/O I/O 112 I/O I/O 113 I/O I/O 42 A54SX32 A54SX08 Function Pin Number Function GND 113 I/O 114 I/O 115 V I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 V 121 CCA V 122 CCR I/O 123 I/O 124 I/O 125 CLKA I/O 126 CLKB I/O 127 ...

Page 43

...

Page 44

... I/O I/O 30 I/O I/O 31 I/O I CCI CCI CCA CCA 34 I/O I/O 35 I/O I/O 36 I/O I/O 37 I/O I/O 38 I/O I/O 39 I/O I I/O 41 I/O I I/O 43 I/O I/O 44 GND GND 44 A54SX32 A54SX08 Function Pin Number Function GND 45 TDI, I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I I/O 53 TMS CCI I I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 PRB, I/O GND 65 GND V 66 ...

Page 45

... CCA CCA 123 GND GND 124 V V CCI CCI 125 I/O I/O 126 I/O I/O 127 I/O I/O 128 I/O I/O 129 I/O I/O 130 I/O I/O 131 NC I/O 132 NC I/O A54SX32 A54SX08 Function Pin Number Function GND 133 GND I/O 134 I/O 135 I/O 136 I/O 137 I/O 138 I/O 139 I/O 140 V I/O 141 V 142 CCA V 143 CCI I/O 144 I/O 145 I/O 146 ...

Page 46

100 1 46 (continued) 100-Pin VQFP v3 ...

Page 47

... I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 I/O 82 I/O 83 PRB, I CCA GND CCR I/O 88 HCLK 89 I/O 90 I/O 91 I CCI I/O 95 I/O 96 I/O 97 I/O 98 TDO, I/O 99 I/O 100 v3.1 A54SX16 A54SX08 A54SX16P Function Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCA CCA V V CCI CCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I CCA CCA GND GND GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ...

Page 48

313-Pin PBGA (Top View ...

Page 49

A54SX32 Pin Number Function Pin Number A1 GND AC15 A3 NC AC17 A5 I/O AC19 A7 I/O ...

Page 50

A54SX32 Pin Number Function Pin Number K10 I/O K12 I/O K14 I/O K16 I/O K18 I/O N11 K20 V N13 CCA K22 I/O N15 ...

Page 51

329-Pin PBGA (Top View ...

Page 52

A54SX32 Pin Number Function Pin Number A1 GND AA23 A2 GND AB1 A3 V AB2 CCI A4 NC AB3 A5 I/O AB4 A6 I/O AB5 A7 V AB6 CCI A8 NC ...

Page 53

A54SX32 Pin Number Function Pin Number G4 I/O L22 G20 I/O L23 G21 I/O G22 I/O G23 ...

Page 54

144-Pin FBGA (Top View (Continued ...

Page 55

... GND G7 GND G8 V CCI G9 I/O G10 I/O G11 I/O G12 I/O H1 I/O H2 I/O H3 I CCA H6 V CCA H7 V CCI H8 V CCI H9 V CCA H10 I/O H11 I/O H12 V CCR v3.1 A54SX08 Pin Number Function J1 I/O J2 I/O J3 I/O J4 I/O J5 I/O J6 PRB, I/O J7 I/O J8 I/O J9 I/O J10 I/O J11 I/O J12 V CCA K1 I/O K2 I/O K3 I/O K4 I/O K5 I/O K6 I/O K7 GND K8 I/O K9 ...

Page 56

... Table 1 on page order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production.” The definition of these categories ...

Page 57

Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 955 East Arques Avenue Dunlop House, Riverside Way Sunnyvale, California 94086 Camberley, Surrey GU15 3YL ...

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