A54SX08-1BG208 ETC1 [List of Unclassifed Manufacturers], A54SX08-1BG208 Datasheet - Page 22

• Manufacturer Part Number: A54SX08-1BG208
• Description: 54SX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

5 4S X T i m i n g M o de l *
H a r d- Wi r e d C lo c k
External Set-Up
Clock-to-Out (Pin-to-Pin)
22
Hard-Wired
Clock
Routed
*Values shown for A54SX08-3, worst-case commercial conditions.
Clock
F
F
I/O Module
MAX
HMAX
t
RCKH
t
HCKH
= 250 MHz
Input Delays
= 320 MHz
= 1.5 ns (100% Load)
= t
= 1.5 + 0.3 + 0.5 – 1.0 = 1.3 ns
= t
= 1.0 + 0.8 + 0.3 + 1.6 = 3.7 ns
t
= 1.0 ns
INY
INY
HCKH
= 1.5 ns
t
SUD
t
+ t
HD
+ t
IRD1
= 0.0 ns
= 0.5 ns
RCO
+ t
+ t
t
SUD
IRD2
RD1
– t
= 0.6 ns
t
+ t
Register
RCO
D
HCKH
Cell
DHL
= 0.8 ns
Q
Internal Delays
Combinatorial
t
PD
t
RD1
Cell
=0.6 ns
= 0.3 ns
v3.1
R o u t ed C lo ck
External Set-Up = t
Clock-to-Out (Pin-to-Pin)
t
RCO
Register
D
t
t
t
RD1
RD8
RD4
= 0.8 ns
Cell
Predicted
Routing
Delays
= 0.3 ns
Q
= 1.9 ns
= 1.0 ns
= 1.5 + 0.3 + 0.5 – 1.5 = 0.8 ns
= t
= 1.52+ 0.8 + 0.3 + 1.6 = 4.2 ns
t
RD1
INY
RCKH
= 0.3 ns
+ t
+ t
I/O Module
IRD1
RCO
+ t
+ t
Output Delays
t
5 4 S X F a m i l y F P G A s
t
DHL
ENZH
SUD
I/O Module
RD1
t
DHL
= 1.6 ns
– t
= 2.3 ns
+ t
= 1.6 ns
RCKH
DHL