A54SX08-1BG208 ETC1 [List of Unclassifed Manufacturers], A54SX08-1BG208 Datasheet - Page 6

• Manufacturer Part Number: A54SX08-1BG208
• Description: 54SX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Figure 4 • Cluster Organization
Ro ut in g Re so u r ce s
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters
page
the number of antifuses required to complete a circuit,
ensuring the highest possible performance.
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering maximum pin-to-pin propagation of 0.4 ns.
6
7). This routing architecture also dramatically reduces
Internal Logic
Connect
CLKA,
CLKB,
Direct
HCLK
Input
Cluster 1
Type 1 SuperCluster
CKS
S0
Data Input
Routed
(Figure 5
R-Cell
CKP
S1
D
and
Cluster 2
PSETB
CLRB
Figure 6 on
Q
Y
v3.1
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100 percent
automatic place and route software to minimize signal
propagation delays.
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hard wired from
the HCLK buffer to the clock select MUX in each R-cell. This
provides a fast propagation path for the clock signal,
enabling the 3.7 ns clock-to-out (pin-to-pin) performance of
the SX devices. The hard-wired clock is tuned to provide
clock skew as low as 0.25 ns. The remaining two clocks
(CLKA, CLKB) are global clocks that can be sourced from
external pins or from internal logic signals within the SX
device.
D0
D1
D2
D3
DB
Cluster 2
Type 2 SuperCluster
C-Cell
A0
B0
Sa
Cluster 1
A1
5 4 S X F a m i l y F P G A s
B1
Sb
Y