A54SX08-1BG208 ETC1 [List of Unclassifed Manufacturers], A54SX08-1BG208 Datasheet - Page 4

• Manufacturer Part Number: A54SX08-1BG208
• Description: 54SX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

S X F a m i l y A r ch i t e c tu r e
The SX family architecture was designed to satisfy
next-generation performance and integration requirements
for production-volume designs in a broad range of
applications.
P r o g r a m m a b l e I n t e r c o nn e c t E l e m e n t
The SX family provides efficient use of silicon by locating the
routing interconnect resources between the Metal 2 (M2)
and Metal 3 (M3) layers
eliminates the channels of routing and interconnect
resources between logic modules (as implemented on SRAM
FPGAs and previous generations of antifuse FPGAs), and
enables the entire floor of the device to be spanned with an
uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
Figure 1 • SX Family Interconnect Elements
Lo g ic M o du le D es ig n
The
“sea-of-modules” architecture because the entire floor of
the device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. Actel’s SX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
4
SX
family
Tungsten Plug
Contact
architecture
Routing Tracks
(Figure
Metal 2
Silicon Substrate
Metal 1
is
1). This completely
Metal 3
described
as
a
v3.1
antifuse interconnect elements, which are embedded
between the M2 and M3 layers. The antifuses are normally
open circuit and, when programmed, form a permanent
low-impedance connection.
The extremely small size of these interconnect elements
gives the SX family abundant routing resources and provides
excellent protection against design pirating. Reverse
engineering is virtually impossible because it is extremely
difficult
unprogrammed antifuses, and there is no configuration
bitstream to intercept.
Additionally, the interconnect (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable (using the S0 and S1
lines) control signals
registers feature programmable clock polarity selectable on
a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized functions
into the SX FPGA. The clock source for the R-cell can be
chosen from either the hard-wired clock or the routed clock.
to
distinguish
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
(Figure 2 on page
Tungsten Plug Via
between
5 4 S X F a m i l y F P G A s
programmed
5). The R-cell
and