A54SX08-1BG208 ETC1 [List of Unclassifed Manufacturers], A54SX08-1BG208 Datasheet - Page 34

• Manufacturer Part Number: A54SX08-1BG208
• Description: 54SX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

P i n D e s c r i p ti o n
CLKA/B
These pins are 3.3V/5.0V PCI/TTL clock inputs for clock
distribution networks. The clock input is buffered prior to
clocking the R-cells. If not used, this pin must be set LOW or
HIGH on the board. It must not be left floating. (For
A54SX72A, these clocks can be configured as bidirectional.)
GND
LOW supply voltage.
HCLK
This pin is the 3.3V/5.0V PCI/TTL clock input for sequential
modules. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or HIGH
on the board. It must not be left floating.
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL, LVTTL,
3.3V PCI or 5.0V PCI specifications. Unused I/O pins are
automatically tristated by the Designer Series software.
NC
This pin is not connected to circuitry within the device.
PRA, I/O
The Probe A pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with
the Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality.
PRB, I/O
The Probe B pin is used to output data from any node within
the device. This diagnostic pin can be used in conjunction
with the Probe A pin to allow real-time diagnostic output of
any signal path within the device. The Probe B pin can be
used as a user-defined I/O when verification has been
completed. The pin’s probe capabilities can be permanently
disabled to protect programmed design confidentiality.
34
Clock A and B
Ground
Dedicated (Hard-wired)
Array Clock
Input/Output
No Connection
Probe A
Probe B
v3.1
TCK
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (refer to
functions as an I/O when the boundary scan state machine
reaches the “logic reset” state.
TDI
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to
when the boundary scan state machine reaches the “logic
reset” state.
TDO
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
on page
scan state machine reaches the “logic reset” state.
TMS
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO). In flexible mode when the TMS
pin is set LOW, the TCK, TDI, and TDO pins are boundary
scan pins (refer to
scan pins are in test mode, they will remain in that mode
until the internal boundary scan state machine reaches the
“logic reset” state. At this point, the boundary scan pins will
be released and will function as regular I/O pins. The “logic
reset” state is reached 5 TCK cycles after the TMS pin is set
HIGH. In dedicated test mode, TMS functions as specified in
the IEEE 1149.1 specifications.
V
Supply voltage for I/Os. See
V
Supply voltage for Array. See
V
Supply voltage for input tolerance (required for internal
biasing) See
CCI
CCA
CCR
8). This pin functions as an I/O when the boundary
Table 2 on page
Table 1 on page
Test Clock
Test Data Input
Test Data Output
Test Mode Select
Supply Voltage
Supply Voltage
Supply Voltage
Table 2 on page
8). This pin functions as an I/O
Table 1 on page
Table 1 on page
8.
Table 2 on page
5 4 S X F a m i l y F P G A s
8). Once the boundary
8.
8.
8). This pin
Table 2