FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 144

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

PIE
The periodic interrupt enable bit is a read/write
bit which allows the periodic-interrupt flag (PF)
bit in Register C to cause the IRQB port to be
driven low. The program writes a "1" to the PIE
bit in order to receive periodic interrupts at the
rate specified by the RS3-RS0 bits in Register
A. A zero in PIE blocks IRQB from being
initiated by a periodic interrupt, but the periodic
flag (PF) is still set at the periodic rate. PIE is
not modified
cleared to "0" by a RESET_DRV.
AIE
The alarm interrupt enable bit is a read/write bit,
which when set to a "1" permits the alarm flag
(AF)
alarm interrupt occurs for each second that the
three time Bytes equal the three alarm bytes
(including a "don't care" alarm code of binary
11XXXXXX). When the AIE bit is a "0", the AF
bit does not initiate an IRQB signal. The
RESET_DRV port clears AIE to
"0". The AIE bit is not affected by any internal
functions.
UIE
The update-ended interrupt enable bit is a
read/write bit which enables the update-end flag
(UF)
REGISTER C (CH) - READ ONLY REGISTER
IRQF
The interrupt request flag is set to a "1" when
one or more of the following are true:
IRQF
MSB
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
b7
bit in Register C to assert
bit in Register C to assert IRQB. The
by any internal function, but is
PF
b6
AF
b5
IRQB.
UF
b4
An
144
RESET_DRV port or the SET bit going high
clears the UIE bit.
RES
Reserved - read as “0”.
DM
The data mode bit indicates whether time and
calendar updates are to use binary or BCD
formats.
processor program and may be read by the
program, but is not modified by any internal
functions or by RESET_DRV. A "1" in DM
signifies binary data, while a "0" in DM specifies
BCD data.
24/12
The 24/12 control bit establishes the format of
the hours byte as either the 24 hour mode if
set to a "1", or the 12 hour mode if cleared to
a "0".
affected by RESET_DRV or any internal
function.
DSE
The daylight savings enable bit is read only and
is always set
daylight savings time option is not available.
Any time the IRQF bit is a "1", the IRQB signal
is driven low. All flag bits are cleared after
Register C is read or by the RESET_DRV port.
PF
The periodic interrupt flag is a read-only bit
which is set to a "1" when a particular edge is
detected on the selected tap of the divider chain.
The RS3-RS0 bits establish the periodic rate.
b3
0
This is a read/write bit which is
The DM bit is written
b2
0
to a "0" to indicate that the
b1
0
by
LSB
b0
0
the
not