FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 32

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

Model 30 Mode
BITS 0 - 1 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
corresponding to the individual data rates. The
data rate select bits are unaffected by a
software reset, and are set to 250 Kbps after a
hardware reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in
the CCR register.
RESET
COND.
See Table 14 for the settings
CHG
DSK
N/A
7
6
0
0
5
0
0
32
4
0
0
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in
the DOR register bit 3.
BITS 4 - 6 UNDEFINED
Always read as a logic "0"
BIT 7 DSKCHG
This bit monitors the pin of the same name and
reflects the opposite value seen on the disk
cable or the value programmed in the Force
Disk
Register LD8:CRC1[1:0]).
DMAEN NOPREC DRATE
3
0
Change
2
0
Register
SEL1
1
1
(see
DRATE
SEL0
0
0
Configuration