FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 154

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

PME SUPPORT
The FDC37B78x offers support for PCI power
management
management event is requested by a PCI
function via the assertion of the nPME signal.
The assertion and deassertion of nPME is
asynchronous to the PCI clock.
FDC37B78x, active transitions on the ring
indicator inputs nRI1 and nRI2 or the nRING
pin, valid NEC infrared remote control frames,
active keyboard-clock edges, active mouse-
clock edges, RTC alarm, and GPIOs GP10-
GP17 can directly assert the nPME signal. In
addition, if the DEVINT_EN bit in the PME_EN 1
Register is set, and if the EN_SMI_PME bit in
the SMI_EN 2 register is set, then any of the
SMI Events can also generate a nPME. See the
SCI/PME and SMI/PME logic diagrams in
FIGURE 5 and FIGURE 6.
nPME functionality is controlled by the runtime
registers
<PM1_BLK>+11h.
PME_EN, globally controls PME Wake-up
at
events
<PM1_BLK>+Ch
The PME Enable bit,
(PMEs).
A
through
In the
power
154
events. When PME_EN is inactive, the nPME
signal can not be asserted. When PME_EN is
asserted, any wake source whose individual
PME Wake Enable register bit is asserted can
cause nPME to become asserted. The PME
Wake Status register indicates which wake
source has asserted the nPME signal. The PME
Status bit, PME_STS, is asserted by active
transitions of PME Wake sources. PME_STS
will become asserted independent of the state of
the global PME enable, PME_EN.
In the FDC37B78x the nPME pin is an open
drain, active low, driver. The FDC37B78x nPME
pin is fully isolated from other external devices
that might pull the PCI nPME signal low; i.e., the
PCI nPME signal is capable of being driven high
externally by another active device or pullup
even when the the FDC37B78x VDD is
grounded, providing VTR power is active. The
FDC37B78x nPME driver sinks 6mA at .55V
max (see section 4.2.1.1 DC Specifications,
page 122, in the PCI Local Bus Specification,
Revision 2.1).