ISL6527 Intersil Corporation, ISL6527 Datasheet - Page 9

• Manufacturer Part Number: ISL6527
• Description: Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
• Manufacturer: Intersil Corporation

Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6527) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
R
locating the poles and zeros of the compensation network:
F
1. Pick gain (R
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
2. Place first zero below filter’s double pole (~75% F
DVOSC
3
LC
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
, C
=
FB
1
----------------------------------------- -
2π x
, C
. The goal of the compensation network is to provide
OSC
2
, and C
0dB
L
1
COMPENSATION DESIGN
COMPARATOR
O
ERROR
AMP
) and adequate phase margin. Phase margin
DETAILED COMPENSATION COMPONENTS
VE/A
ISL6527
x C
2
/R
PWM
3
O
1
) in Figure 5. Use these guidelines for
ZFB
+
-
) for desired converter bandwidth.
-
+
COMP
C2
REFERENCE
REFERENCE
C1
+
-
F
DRIVER
DRIVER
R2
9
ZIN
ESR
=
FB
------------------------------------------ -
2π x ESR x C
ZFB
PHASE
(PARASITIC)
VIN
C3
1
LO
ZIN
R1
R3
ESR
CO
VOUT
O
LC
0dB
1
).
VOUT
, R
and
IN
2
,
ISL6527
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain is constructed on the graph of
Figure 6 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst-case component variations when
determining phase margin.
Component Selection Guidelines
Charge Pump Capacitor Selection
A capacitor across pins CT1 and CT2 is required to create
the proper bias voltage for the ISL6527 when operating the
IC from 3.3V. Selecting the proper capacitance value is
important so that the bias current draw and the current
required by the MOSFET gates do not overburden the
F
F
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
Z1
Z2
100
-20
-40
-60
80
60
40
20
0
and Z
=
=
10
--------------------------------- -
2π
------------------------------------------------------ -
2π x R
MODULATOR
20
IN
×
log
GAIN
R
(
1
to provide a stable, high bandwidth (BW) overall


2
100
R2
------- -
R1
1
×
FZ1
1
+
C


R
2
3
) x C
FLC
1K
P2
FZ2
FREQUENCY (Hz)
3
with the capabilities of the error
FESR
10K
F
F
FP1
P1
P2
100K
=
=
FP2
-------------------------------------------------------- -
2π x R
----------------------------------- -
2π x R
1M
1
2
3
ERROR AMP GAIN
x
x C
COMPENSATION
1
OPEN LOOP
20



LOOP GAIN
C
--------------------- -
C
3
log
10M
1
1
GAIN
x C
+



----------------- -
V OSC
C
V IN
2
2





