ISL6531 Intersil Corporation, ISL6531 Datasheet
ISL6531
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ISL6531 Summary of contents
Page 1
... Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory V and V Termination DDQ TT The ISL6531 provides complete control and protection for dual DC-DC converters optimized for high-performance DDRAM memory applications designed to drive low cost N-channel MOSFETs in synchronous-rectified buck topology to efficiently generate 2.5V V DDQ DDRAM memory, V ...
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... VREF 4 20 FB1 COMP1 18 7 SENSE1 17 VREF_IN GNDA 15 PHASE2 BOOT2 13 UGATE2 12 2 ISL6531 PGND1 LGATE1 PVCC1 OCSET/SD PHASE 1 V2_SD VREF PGOOD N/C FB1 SENSE2 COMP1 N/C SENSE1 VCC LGATE2 VREF_IN PGND2 GNDA GNDA 32 LEAD 5X5 (QFN) TOP VIEW ...
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... Block Diagram PGOOD FB1 COMP1 SENSE1 VREF_IN + VREF - SENSE2 V2_SD 3 ISL6531 OCSET/SD VCC POWER-ON RESET (POR) + SOFT- - 40µA START OVER- CURRENT PWM ERROR COMPARATOR AMP INHIBIT + + - - PWM 0.8V REFERENCE OSCILLATOR o 90 Phase Shift ERROR AMP + - Z f PWM - + Z c INHIBIT PWM COMPARATOR WINDOW ...
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... VREF COMP1 FB1 R FB1 4 ISL6531 PGOOD VCC PGOOD BOOT1 UGATE1 PHASE1 PVCC1 LGATE1 ISL6531 PGND1 D BOOT2 UGATE2 C PHASE2 LGATE2 PGND2 SENSE1 SENSE2 FIGURE 1. TYPICAL APPLICATION FOR ISL6531 D BOOT1 BOOT1 L OUT1 +5V C OUT1 Q 2 BOOT2 Q 3 BOOT2 L OUT2 OUT2 V DDQ ...
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... Upper Gate Source (UGATE1 and 2) Upper Gate Sink (UGATE1 and 2) Lower Gate Source (LGATE1 and 2) Lower Gate Sink (LGATE1 and 2) PROTECTION OCSET/SD Current Source OCSET/SD Disable Voltage 5 ISL6531 Thermal Information Thermal Resistance SOIC Package (Note +0.3V CC QFN Package (Note 2 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Storage Temperature Range ...
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... I PEAK An overcurrent trip cycles the soft-start function. Pulling the OCSET/SD pin to ground resets the ISL6531 and all external MOSFETS are turned off allowing the two output voltage power rails to float. PGOOD A high level on this open-drain output indicates that both the ...
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... V2_SD mode. Functional Description Overview The ISL6531 contains control and drive circuitry for two synchronous buck PWM voltage regulators. Both regulators utilize 5V bootstrapped output topology to allow use of low cost N-Channel MOSFETs. The regulators are driven by ...
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... The only load placed on the V the leakage of the associated signal pins of the DDRAM and memory controller ICs. 8 ISL6531 When the V2_SD input of the ISL6531 is driven high, the V regulator is placed into a “sleep” state. In the sleep state TT the main V VCC (5V) lower MOSFETs being turned off ...
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... LOW. Upon release of the OCSET/SD pin, the IC enters into a soft start cycle which brings both outputs back into regulation. Voltage Monitoring The ISL6531 offers a PGOOD signal that will communicate whether the regulation of both V and V DDQ ±15% of regulation, the V2_SD pin is held low and the bias voltage of the IC is above the POR level ...
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... TT through protection method which allows the converter to sink current as well as source current. Care should be exercised when designing a converter with the ISL6531 when it is known that the converter may sink current. When the converter is sinking current behaving as a boost converter that is regulating its input voltage. This means that the converter is boosting current into the input rail of the regulator ...
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... VIA CONNECTION TO GROUND PLANE FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS The switching components should be placed close to the ISL6531 first. Minimize the length of the connections between the input capacitors and the power switches IN by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible ...
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... The compensation network consists of the error amplifier (internal to the ISL6531) and the impedance networks Z and Z . The goal of the compensation network is to provide FB a closed loop transfer function with the highest 0dB crossing frequency (f ) and adequate phase margin. Phase margin 0dB is the difference between the closed loop phase at f 180 degrees. The equations below relate the compensation network’ ...
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... Given a sufficiently fast control loop design, the ISL6531 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...
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... MOSFET’s body diode. The gate-charge losses are dissipated by the ISL6531 and don't heat the MOSFETs. However, large gate-charge increases the switching interval, t increases the MOSFET switching losses. ...
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... ISL6531 DC-DC Converter Application Circuit Figure 11 shows an application circuit for a DDR SDRAM power supply, including V (+2.5V) and V DDQ Detailed information on the circuit, including a complete Billof-Materials and circuit board description, can be found V2_SD PGOOD VREF VREF_IN C 30 100pF GNDA C 26 5600pF COMP1 100pF 6.34kΩ ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 16 ISL6531 M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE SYMBOL M ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 ISL6531 L32.5x5 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...