ISL6590 Intersil Corporation, ISL6590 Datasheet

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ISL6590

Manufacturer Part Number
ISL6590
Description
Digital Multi-Phase PWM Controller for Core-Voltage Regulation
Manufacturer
Intersil Corporation
Datasheet
Digital Multi-Phase PWM Controller for
Core-Voltage Regulation
Processors that operate above a GHz require fast, intelligent
power systems. The Intersil ISL6590 controller offers
intelligent digital, multi-phase control that provides high
bandwidth, optimal control frequency response, noise
immunity and active transient response control algorithms.
The design is fully scalable for controlling up to six phases,
each featuring the Intersil ISL6580 intelligent power stage.
The user can configure and monitor the power system via
the Asynchronous Serial Interface (ASI). The ISL6590
controller flexibility can be extended with the addition of an
external EEPROM for updating key circuit operating
parameters in the control loop and overall system design.
The digital architecture reduces the design time for
engineers with the use of our software. The software allows
the designer the freedom to choose output stage
components and still achieve optimized system
performance.
The ISL6590 digital controller communicates with the
ISL6580 integrated power stages via 100% digital signaling.
Serial communication allows for separation of the controller
and the power stage, providing placement and layout
freedom to the power stage. The digital controller
implements phase balancing to ensure even distribution of
phase currents. The ISL6590 controller configures the
ISL6580 power stage current limit, VID reference, non-
overlap period, Active Transient Response (ATR) trigger
levels and maximum temperature limit. The digital controller
also monitors the ISL6580 power stage peak currents, over-
temperature fault, input under voltage, output over/under
voltage to ensure proper operation of the power supply.
Pinout
VDD_CORE
NDRIVE1
PWRGD
VDD_IO
OUTEN
VID [0]
VID [1]
VID [2]
VID [3]
VID [4]
VID [5]
PWM1
MCLK
MDO
MCS
MDI
01
16
64
17
ISL6590 (QFN)
TOP VIEW
®
1
Data Sheet
All other trademarks mentioned are the property of their respective owners. Dynamic VID™ is a trademark of Intersil Americas Inc.
49
32
48
33
TEST 2
ATRL
SOC
ERR
VDD_IO
SYS_CLK
VDD_IO
NC
NC
VDD_CORE
NC
NC
IDIG6
PWM6
NDRIVE6
TEST1
1-888-INTERSIL or 321-724-7143
CCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Open Architecture features software programmable
• Intel VR10
• 250kHz to 1MHz switching frequency
• 100% digital control and signaling
• Active Transient Response (ATR) control algorithms for
• Controls up to six ISL6580 intelligent power stages (20A
• Programmable Adaptive voltage positioning (AVP) load
• Configurable control loop parameters (with optional
• Programmable MOSFET dead time control
• High speed voltage and current control loops
• PWRGD and OUTEN
• Serial interface to ISL6580 power stages for system
• 64 Ld 9x9 QFN package
• QFN Package Option
Ordering Information
ISL6590DR
control loop compensation enabling optimal system
performance
- User accessible asynchronous serial interface
- 6-bit Dynamic VID™
- Output voltage regulation range of 0.8375V to 1.600Vdc
minimized voltage droop and overshoot
per phase, 120A total system current)
line
external EEPROM)
monitoring and configuration
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
- QFN Near Chip Scale Package Footprint; Improves
PART NUMBER
Flat No Leads - Product Outline
PCB Efficiency, Thinner in Profile.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
April 2003
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
TEMP. (
0 to 85
o
C)
64 Ld 9x9 QFN L64.9x9-S
PACKAGE
ISL6590
FN9061
PKG. NO.

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ISL6590 Summary of contents

Page 1

... Digital Multi-Phase PWM Controller for Core-Voltage Regulation Processors that operate above a GHz require fast, intelligent power systems. The Intersil ISL6590 controller offers intelligent digital, multi-phase control that provides high bandwidth, optimal control frequency response, noise immunity and active transient response control algorithms. ...

Page 2

... ISL6590 ATRH ATRL OSC_IN OSC_OUT PWM IDIG NDRIVE TEST1 TEST2 TEST3 TEST4 MDO MDI MCS MCLK PWM IDIG NDRIVE GND 2 ISL6590 3 2.5 V VDD VDRIVE VCC VREF V SENP ATRH VSENN ATRL ISL6580 ERR ISENSE SOC SCLK VSW SDATA CLK NGATE PWM ...

Page 3

... PWRGD, V Open drain, 6mA drive OH PWRGD, V Open drain, 6mA drive OL OSC_OUT internal pull-up/down resistors, 10mA drive OH OSC_OUT internal pull-up/down resistors, 10mA drive OL 3 ISL6590 Thermal Information Thermal Resistance θ θ JA-0 LFPM AIR θ JA-100 LFPM AIR θ ...

Page 4

... Falling ddio ddcore Rising ddcore Falling Feedback Control Memory Bus MUX Control/ Non-Volatile Status SPI EEPOM Registers Interface MHz Memory State Mapped Registers Machine FIGURE 1. ISL6590 BLOCK DIAGRAM Unless Otherwise Specified (Continued) A MIN TYP MAX 1 2.55 0 1.4 - ...

Page 5

... Active Transient Response High input signal from the ISL6580 indicating a voltage droop on the converter output. ISL6580 and ISL6590 controller. Serial digital bus clock supplied for the 16.67MHz clocking that accompanies SDATA via the Backside serial bus. Asynchronous Serial Interface Transmit Asynchronous Serial Interface Receive Only used if part is using a crystal to generate the system clock ...

Page 6

... For more information on the power stage, consult the ISL6580 data sheet. Block Diagram Overview The ISL6590 contains functionality to control power stages with PWM core voltage regulation. The blocks described follow the block diagram shown in Figure 1. For additional help it would be useful to reference the block diagram of the ISL6580, which is located in the ISL6580 data sheet ...

Page 7

... It is not possible to predict when the serial data will begin to transfer on the IDIG bus start bit is used to notify the ISL6590 that data is coming. The start bit is followed by the six data bits in descending order from the MSB. A bit is transferred every two SYSCLK cycles. Since the PWM ...

Page 8

... ATRH or ATRL indicator signals when the event occurs. The ATRH and ATRL trip levels are offsets from the VID voltage and are set in ISL6590 register 0883h, each with a 4-bit word. The ATRH, ATRL, and VID values from the ISL6590 memory are sent to the designated ISL6580’ ...

Page 9

... Soft Start process is also applied to dynamic VID changes Custom VID The ISL6590 has additional registers for a custom VID table created and stored in memory locations 0940-097F OUT ...

Page 10

... The serial data is constructed with a start bit, eight data bits, and a stop bit. Parity is not supported. 10 ISL6590 Controller specific serial interface commands are restricted to reads and writes of the controller memory map. Details are provided in Tables 2-5. TABLE 2. ASYNCHRONOUS SERIAL INTERFACE ...

Page 11

... Data Setup Data Hold TYPICAL UNITS 480 ns 240 ns 240 ns 480 ns 720 DSU DH KH FIGURE 6. ISL6590 DATA WRITE TIMING TABLE 8. DATA WRITE TIMING PARAMETER TYPICAL t 45 DSU SPH t 62.5 p FIGURE 7. DATA READ TIMING TABLE 9. DATA READ TIMING ...

Page 12

... Address: Register 12 ISL6590 8 Clocks R/W Dead Ack Data Byte (to ISL6580) Cycle (from ISL6580 ) FIGURE 8. ISL6590 WRITE PROTOCOL R/W Dead Ack Data Byte (from ISL6580) Cycle (from ISL6580 ) FIGURE 9. ISL6590 READ PROTOCOL Dead Ack Cycle (from ISL6580 ) 8 Clocks Dead Ack Cycle (from ISL6580 ) Stop Stop ...

Page 13

... The rate of transfer is set by the serial clock divider register. Background polling of ISL6580 fault registers is performed using the BSB. The fault information is written to the ISL6590 local copies of the ISL6580 fault registers. ISL6580 control registers can be written to or read back from the ISL6590 memory via the BSB. Startup Process ...

Page 14

... PWM and NDRIVE signals are held at ground and all MOSFETs are OFF. Duty Cycle Limit The ISL6590 limits the on time of the upper FETs. The system designer can set the maximum ON time with PowerCode software The value is put percentage. If the duty cycle reaches this percentage, the top side FET turns off until the next cycle ...

Page 15

... FIGURE 14. DIGITAL CONTROL LOOP BLOCK DIAGRAM The ISL6580 subtracts a reference from the output voltage to produce an error voltage. It converts the error voltage bit digital number and sends it to the ISL6590 controller. The controller processes the error number numerically to provide gain (Proportional), phase lag (Integration) and phase lead (Derivative) functions ...

Page 16

... Kp, Ki and Kd factors. the software will calculate and display the frequency response of the feedback and the closed loop system. FIGURE 17. DESIGN PARAMETER INPUT WINDOW 16 ISL6590 FIGURE 18. SMALL SIGNAL DESIGN WINDOW FIGURE 19. BODE PLOT F = Frequency of first zero Z1 ...

Page 17

... FIGURE 22. TYPICAL RESPONSE TO A LOAD TRANSIENT User Interface Software The ISL6590 controller and the ISL6580 intelligent power stage have programmable values that can be changed using the User Interface Software. The loop configuration and system performance is adjusted using the software. The use ...

Page 18

... FIGURE 23. PRIMARION POWERCODE LOADLINE AND ATR SETTINGS FIGURE 24. PRIMARION POWERCODE LOOP RESPONSE SETTINGS 18 ISL6590 FIGURE 25. PRIMARION POWERCODE MONITOR WINDOW FIGURE 26. PRIMARION POWERCODE DESIGN INPUTS FIGURE 27. PRIMARION POWERCODE DUTY CYCLE LIMIT SELECTION ...

Page 19

... Feedback Loop Control 0202 Open Loop PID (LSB) 0203 Open Loop PID (MSB) 0204 – 0205 Reserved 0206 ATR Control 0207 Phases Used 0208 Phase Enables 209 Reserved 19 ISL6590 TABLE 11. ISL6590 MEMORY MAP NAME R/W/S SIZE (NOTE 1) (BITS) 1 R/W/Ws SIZE (bits ...

Page 20

... On Time – Phase 6 (upper 8 bits) 0236 On Time – Phase 7 (upper 8 bits) 0237 On Time – Phase 8 (upper 8 bits) 0238 – 02FF Reserved 0300 - 03FF Reserved 0400 – 07FF Broadcast Write Memory Map 0400 Reserved 20 ISL6590 TABLE 11. ISL6590 MEMORY MAP (Continued) NAME R/W/S SIZE (NOTE 1) (BITS) R R/W 8 R/W ...

Page 21

... VID_IN Table Select 0803 VID_OUT Table Select 0804 OffOn Non-Overlap Driver Control 0805 OnOff Non-Overlap Driver Control 0806 Duty Limit 0807 System Configuration 0808 Reserved 21 ISL6590 TABLE 11. ISL6590 MEMORY MAP (Continued) NAME R/W/S SIZE (NOTE 1) (BITS ...

Page 22

... General Control Registers Phase # Independent Compensation Parameters 0900 Kp AVP 0901 Kd AVP 0902 Kp PID 0903 Ki PID 0904 Kd Transient Recovery 0905 Vos AVP 0906 Ios AVP 0907 Kfp PID 0908 Kfd PID 22 ISL6590 TABLE 11. ISL6590 MEMORY MAP (Continued) NAME R/W/S SIZE (NOTE 1) (BITS) R/W 5 R/W 5 R/W 5 R/W 7 R/W 6 R/W 2 R/W 8 R/W 5 ...

Page 23

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 23 ISL6590 TABLE 11. ISL6590 MEMORY MAP (Continued) NAME PKG. NO L64.9x9 R/W/S ...

Page 24

... A) 6 INDEX AREA (Nd-1)Xe REF. BOTTOM VIEW SECTION "C-C" SCALE: NONE TERMINAL TIP FOR EVEN TERMINAL/SIDE 24 ISL6590 L64.9x9-S 64 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE SYMBOL E/2 E1 ...

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